diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
| commit | dafec4a51542b76a926b390f0cafa6c715a54c49 (patch) | |
| tree | b9088b609725b87ec1ef5f6a5359b3454ed4519c /tests/long | |
| parent | c661cc75eca97989d72c513550b7a63e995a3982 (diff) | |
| download | gem5-dafec4a51542b76a926b390f0cafa6c715a54c49.tar.xz | |
stats: update and fix e273e86a873d
Diffstat (limited to 'tests/long')
54 files changed, 38983 insertions, 3259 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 605ec955f..e76fc661c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.847227 # Nu sim_ticks 2847227406000 # Number of ticks simulated final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172654 # Simulator instruction rate (inst/s) -host_op_rate 209070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3861033235 # Simulator tick rate (ticks/s) -host_mem_usage 617124 # Number of bytes of host memory used -host_seconds 737.43 # Real time elapsed on the host +host_inst_rate 111277 # Simulator instruction rate (inst/s) +host_op_rate 134747 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2488466073 # Simulator tick rate (ticks/s) +host_mem_usage 617520 # Number of bytes of host memory used +host_seconds 1144.17 # Real time elapsed on the host sim_insts 127319545 # Number of instructions simulated sim_ops 154173476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -441,9 +441,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6777 system.cpu0.dtb.walker.walkRequestOrigin::total 75197 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17339980 # DTB read hits +system.cpu0.dtb.read_hits 17339981 # DTB read hits system.cpu0.dtb.read_misses 61941 # DTB read misses -system.cpu0.dtb.write_hits 14540399 # DTB write hits +system.cpu0.dtb.write_hits 14540400 # DTB write hits system.cpu0.dtb.write_misses 6479 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -454,12 +454,12 @@ system.cpu0.dtb.align_faults 1354 # Nu system.cpu0.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 521 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17401921 # DTB read accesses -system.cpu0.dtb.write_accesses 14546878 # DTB write accesses +system.cpu0.dtb.read_accesses 17401922 # DTB read accesses +system.cpu0.dtb.write_accesses 14546879 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31880379 # DTB hits +system.cpu0.dtb.hits 31880381 # DTB hits system.cpu0.dtb.misses 68420 # DTB misses -system.cpu0.dtb.accesses 31948799 # DTB accesses +system.cpu0.dtb.accesses 31948801 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -593,9 +593,9 @@ system.cpu0.tickCycles 128530134 # Nu system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped system.cpu0.dcache.tags.replacements 715130 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30394668 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 715642 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.471890 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.471892 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356009000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.249385 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977050 # Average percentage of cache occupancy @@ -605,22 +605,22 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 126 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63780149 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63780149 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15810331 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15810331 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13424811 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13424811 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13424812 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320440 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 320440 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365226 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 365226 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361080 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 361080 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29235142 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29235142 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29555582 # number of overall hits -system.cpu0.dcache.overall_hits::total 29555582 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 29235144 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29235144 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29555584 # number of overall hits +system.cpu0.dcache.overall_hits::total 29555584 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 463723 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 463723 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 580901 # number of WriteReq misses @@ -649,20 +649,20 @@ system.cpu0.dcache.demand_miss_latency::cpu0.data 16499002500 system.cpu0.dcache.demand_miss_latency::total 16499002500 # number of demand (read+write) miss cycles system.cpu0.dcache.overall_miss_latency::cpu0.data 16499002500 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 16499002500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274054 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16274054 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005712 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14005712 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16274055 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16274055 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14005713 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14005713 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456923 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 456923 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386533 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386533 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381647 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381647 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30279766 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30279766 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30736689 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30736689 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 30279768 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30279768 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30736691 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30736691 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028495 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.028495 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041476 # miss rate for WriteReq accesses diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index c94a5f66f..9c380c00f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.858505 # Nu sim_ticks 2858505242500 # Number of ticks simulated final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171882 # Simulator instruction rate (inst/s) -host_op_rate 207819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4390877747 # Simulator tick rate (ticks/s) -host_mem_usage 578076 # Number of bytes of host memory used -host_seconds 651.01 # Real time elapsed on the host +host_inst_rate 125507 # Simulator instruction rate (inst/s) +host_op_rate 151748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3206183180 # Simulator tick rate (ticks/s) +host_mem_usage 578080 # Number of bytes of host memory used +host_seconds 891.56 # Real time elapsed on the host sim_insts 111897168 # Number of instructions simulated sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -403,9 +403,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24710832 # DTB read hits +system.cpu.dtb.read_hits 24710833 # DTB read hits system.cpu.dtb.read_misses 59358 # DTB read misses -system.cpu.dtb.write_hits 19424403 # DTB write hits +system.cpu.dtb.write_hits 19424404 # DTB write hits system.cpu.dtb.write_misses 6793 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -416,12 +416,12 @@ system.cpu.dtb.align_faults 1526 # Nu system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24770190 # DTB read accesses -system.cpu.dtb.write_accesses 19431196 # DTB write accesses +system.cpu.dtb.read_accesses 24770191 # DTB read accesses +system.cpu.dtb.write_accesses 19431197 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44135235 # DTB hits +system.cpu.dtb.hits 44135237 # DTB hits system.cpu.dtb.misses 66151 # DTB misses -system.cpu.dtb.accesses 44201386 # DTB accesses +system.cpu.dtb.accesses 44201388 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -551,9 +551,9 @@ system.cpu.tickCycles 228131430 # Nu system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 842468 # number of replacements system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42541757 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.465915 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.465917 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy @@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175934547 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175934547 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23016254 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23016254 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18262412 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18262412 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18262413 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41278666 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41278666 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41634968 # number of overall hits -system.cpu.dcache.overall_hits::total 41634968 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 41278668 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41278668 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41634970 # number of overall hits +system.cpu.dcache.overall_hits::total 41634970 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses @@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 43652936479 system.cpu.dcache.demand_miss_latency::total 43652936479 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 43652936479 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 43652936479 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23510096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23510096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18810393 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18810393 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23510097 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23510097 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18810394 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18810394 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 526172 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 526172 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466016 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 466016 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460207 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460207 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42320489 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42320489 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42846661 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42846661 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42320491 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42320491 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42846663 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42846663 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021006 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.021006 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029132 # miss rate for WriteReq accesses diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8cc8c8d31..11b022e8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92547 # Simulator instruction rate (inst/s) -host_op_rate 112251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2318051416 # Simulator tick rate (ticks/s) +host_inst_rate 63021 # Simulator instruction rate (inst/s) +host_op_rate 76439 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1578508192 # Simulator tick rate (ticks/s) host_mem_usage 579360 # Number of bytes of host memory used -host_seconds 1222.09 # Real time elapsed on the host +host_seconds 1794.65 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -395,9 +395,9 @@ system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7544 system.cpu.checker.dtb.walker.walkRequestOrigin::total 17252 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24576303 # DTB read hits +system.cpu.checker.dtb.read_hits 24576304 # DTB read hits system.cpu.checker.dtb.read_misses 8296 # DTB read misses -system.cpu.checker.dtb.write_hits 19632669 # DTB write hits +system.cpu.checker.dtb.write_hits 19632670 # DTB write hits system.cpu.checker.dtb.write_misses 1412 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -408,12 +408,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24584599 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19634081 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24584600 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19634082 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44208972 # DTB hits +system.cpu.checker.dtb.hits 44208974 # DTB hits system.cpu.checker.dtb.misses 9708 # DTB misses -system.cpu.checker.dtb.accesses 44218680 # DTB accesses +system.cpu.checker.dtb.accesses 44218682 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -568,9 +568,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25410889 # DTB read hits +system.cpu.dtb.read_hits 25410890 # DTB read hits system.cpu.dtb.read_misses 62740 # DTB read misses -system.cpu.dtb.write_hits 19865162 # DTB write hits +system.cpu.dtb.write_hits 19865163 # DTB write hits system.cpu.dtb.write_misses 9628 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -581,12 +581,12 @@ system.cpu.dtb.align_faults 362 # Nu system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25473629 # DTB read accesses -system.cpu.dtb.write_accesses 19874790 # DTB write accesses +system.cpu.dtb.read_accesses 25473630 # DTB read accesses +system.cpu.dtb.write_accesses 19874791 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45276051 # DTB hits +system.cpu.dtb.hits 45276053 # DTB hits system.cpu.dtb.misses 72368 # DTB misses -system.cpu.dtb.accesses 45348419 # DTB accesses +system.cpu.dtb.accesses 45348421 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -690,7 +690,7 @@ system.cpu.itb.accesses 66008446 # DT system.cpu.numCycles 278423951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken @@ -704,21 +704,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 188 # system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking @@ -728,7 +728,7 @@ system.cpu.decode.BranchMispred 467954 # Nu system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running @@ -759,14 +759,14 @@ system.cpu.iq.iqSquashedInstsIssued 260968 # Nu system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -775,7 +775,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available @@ -848,7 +848,7 @@ system.cpu.iq.FU_type_0::total 143038678 # Ty system.cpu.iq.rate 0.513744 # Inst issue rate system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads @@ -892,30 +892,30 @@ system.cpu.iew.exec_stores 20827406 # Nu system.cpu.iew.exec_rate 0.510511 # Inst execution rate system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63237138 # num instructions producing a value -system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value +system.cpu.iew.wb_producers 63237137 # num instructions producing a value +system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle system.cpu.commit.committedInsts 113255406 # Number of instructions committed system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -961,11 +961,11 @@ system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389119867 # The number of ROB reads +system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389119868 # The number of ROB reads system.cpu.rob.rob_writes 292294903 # The number of ROB writes system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 113100501 # Number of Instructions Simulated system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated @@ -973,19 +973,19 @@ system.cpu.cpi 2.461739 # CP system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155524958 # number of integer regfile reads +system.cpu.int_regfile_reads 155524954 # number of integer regfile reads system.cpu.int_regfile_writes 88488763 # number of integer regfile writes system.cpu.fp_regfile_reads 9529 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502156064 # number of cc regfile reads +system.cpu.cc_regfile_reads 502156067 # number of cc regfile reads system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads +system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy @@ -995,22 +995,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits -system.cpu.dcache.overall_hits::total 39152130 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits +system.cpu.dcache.overall_hits::total 39152132 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses @@ -1037,20 +1037,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index fccb40933..1ded9ce83 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825951 # Number of seconds simulated -sim_ticks 2825951018000 # Number of ticks simulated -final_tick 2825951018000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825960 # Number of seconds simulated +sim_ticks 2825959731500 # Number of ticks simulated +final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126581 # Simulator instruction rate (inst/s) -host_op_rate 153564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2973571752 # Simulator tick rate (ticks/s) -host_mem_usage 617520 # Number of bytes of host memory used -host_seconds 950.36 # Real time elapsed on the host -sim_insts 120297223 # Number of instructions simulated -sim_ops 145940268 # Number of ops (including micro ops) simulated +host_inst_rate 71367 # Simulator instruction rate (inst/s) +host_op_rate 86573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1679006506 # Simulator tick rate (ticks/s) +host_mem_usage 618544 # Number of bytes of host memory used +host_seconds 1683.11 # Real time elapsed on the host +sim_insts 120118276 # Number of instructions simulated +sim_ops 145712235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1286144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1281192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8384576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 188912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 582932 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 428544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12155436 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1286144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 188912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1475056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8692480 # Number of bytes written to this memory +system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8710044 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20539 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3020 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192785 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135820 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 455119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 453367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2966993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 206278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 151646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4301361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 455119 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 521968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3075949 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3082164 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3075949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 455119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 459568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2966993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 206292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 151646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7383525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 192786 # Number of read requests accepted -system.physmem.writeReqs 140211 # Number of write requests accepted -system.physmem.readBursts 192786 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12328960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8722752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12155500 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8710044 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198102 # Number of read requests accepted +system.physmem.writeReqs 144340 # Number of write requests accepted +system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11498 # Per bank write bursts -system.physmem.perBankRdBursts::1 11843 # Per bank write bursts -system.physmem.perBankRdBursts::2 12508 # Per bank write bursts -system.physmem.perBankRdBursts::3 12790 # Per bank write bursts -system.physmem.perBankRdBursts::4 14191 # Per bank write bursts -system.physmem.perBankRdBursts::5 11869 # Per bank write bursts -system.physmem.perBankRdBursts::6 11798 # Per bank write bursts -system.physmem.perBankRdBursts::7 11857 # Per bank write bursts -system.physmem.perBankRdBursts::8 12385 # Per bank write bursts -system.physmem.perBankRdBursts::9 12638 # Per bank write bursts -system.physmem.perBankRdBursts::10 11524 # Per bank write bursts -system.physmem.perBankRdBursts::11 10795 # Per bank write bursts -system.physmem.perBankRdBursts::12 11419 # Per bank write bursts -system.physmem.perBankRdBursts::13 12202 # Per bank write bursts -system.physmem.perBankRdBursts::14 11695 # Per bank write bursts -system.physmem.perBankRdBursts::15 11628 # Per bank write bursts -system.physmem.perBankWrBursts::0 8335 # Per bank write bursts -system.physmem.perBankWrBursts::1 8752 # Per bank write bursts -system.physmem.perBankWrBursts::2 9292 # Per bank write bursts -system.physmem.perBankWrBursts::3 9229 # Per bank write bursts -system.physmem.perBankWrBursts::4 7962 # Per bank write bursts -system.physmem.perBankWrBursts::5 8394 # Per bank write bursts -system.physmem.perBankWrBursts::6 8300 # Per bank write bursts -system.physmem.perBankWrBursts::7 8278 # Per bank write bursts -system.physmem.perBankWrBursts::8 8796 # Per bank write bursts -system.physmem.perBankWrBursts::9 9162 # Per bank write bursts -system.physmem.perBankWrBursts::10 8546 # Per bank write bursts -system.physmem.perBankWrBursts::11 8147 # Per bank write bursts -system.physmem.perBankWrBursts::12 8256 # Per bank write bursts -system.physmem.perBankWrBursts::13 8410 # Per bank write bursts -system.physmem.perBankWrBursts::14 8295 # Per bank write bursts -system.physmem.perBankWrBursts::15 8139 # Per bank write bursts +system.physmem.perBankRdBursts::0 12421 # Per bank write bursts +system.physmem.perBankRdBursts::1 12320 # Per bank write bursts +system.physmem.perBankRdBursts::2 12949 # Per bank write bursts +system.physmem.perBankRdBursts::3 12687 # Per bank write bursts +system.physmem.perBankRdBursts::4 14539 # Per bank write bursts +system.physmem.perBankRdBursts::5 12136 # Per bank write bursts +system.physmem.perBankRdBursts::6 12666 # Per bank write bursts +system.physmem.perBankRdBursts::7 12482 # Per bank write bursts +system.physmem.perBankRdBursts::8 12195 # Per bank write bursts +system.physmem.perBankRdBursts::9 12078 # Per bank write bursts +system.physmem.perBankRdBursts::10 11738 # Per bank write bursts +system.physmem.perBankRdBursts::11 11022 # Per bank write bursts +system.physmem.perBankRdBursts::12 11908 # Per bank write bursts +system.physmem.perBankRdBursts::13 13049 # Per bank write bursts +system.physmem.perBankRdBursts::14 12095 # Per bank write bursts +system.physmem.perBankRdBursts::15 11669 # Per bank write bursts +system.physmem.perBankWrBursts::0 9112 # Per bank write bursts +system.physmem.perBankWrBursts::1 9127 # Per bank write bursts +system.physmem.perBankWrBursts::2 9607 # Per bank write bursts +system.physmem.perBankWrBursts::3 9172 # Per bank write bursts +system.physmem.perBankWrBursts::4 8420 # Per bank write bursts +system.physmem.perBankWrBursts::5 8729 # Per bank write bursts +system.physmem.perBankWrBursts::6 8984 # Per bank write bursts +system.physmem.perBankWrBursts::7 8803 # Per bank write bursts +system.physmem.perBankWrBursts::8 8716 # Per bank write bursts +system.physmem.perBankWrBursts::9 8606 # Per bank write bursts +system.physmem.perBankWrBursts::10 8527 # Per bank write bursts +system.physmem.perBankWrBursts::11 8118 # Per bank write bursts +system.physmem.perBankWrBursts::12 8733 # Per bank write bursts +system.physmem.perBankWrBursts::13 9183 # Per bank write bursts +system.physmem.perBankWrBursts::14 8560 # Per bank write bursts +system.physmem.perBankWrBursts::15 8024 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2825950731000 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 2825959428000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189120 # Read request sizes (log2) +system.physmem.readPktSize::6 194436 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 135820 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4480 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 139949 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,162 +188,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.966703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.563892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.532977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48504 54.60% 54.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17119 19.27% 73.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5692 6.41% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3330 3.75% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2666 3.00% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1452 1.63% 88.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 904 1.02% 89.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1002 1.13% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8169 9.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88838 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6725 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.644610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 576.008815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6723 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6725 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.266617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.732165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.286650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5583 83.02% 83.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 392 5.83% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 83 1.23% 90.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 55 0.82% 90.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 273 4.06% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 27 0.40% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.33% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.27% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 21 0.31% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.18% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 148 2.20% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.13% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6725 # Writes before turning the bus around for reads -system.physmem.totQLat 6328126220 # Total ticks spent queuing -system.physmem.totMemAccLat 9940126220 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 963200000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32849.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads +system.physmem.totQLat 6678126737 # Total ticks spent queuing +system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51599.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.08 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.86 # Average write queue length when enqueuing -system.physmem.readRowHits 160949 # Number of row buffer hits during reads -system.physmem.writeRowHits 79145 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes -system.physmem.avgGap 8486414.99 # Average gap between requests -system.physmem.pageHitRate 72.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 340562880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 185823000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 767153400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 444152160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79601761125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625743658250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891660385775 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.389284 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704476978140 # Time in different power states -system.physmem_0.memoryStateTime::REF 94364660000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 165316 # Number of row buffer hits during reads +system.physmem.writeRowHits 80625 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes +system.physmem.avgGap 8252373.91 # Average gap between requests +system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.423201 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states +system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27109359860 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 331052400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180633750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 735430800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 439026480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184577274960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79228268055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626071283750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891562970195 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.354813 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705022466825 # Time in different power states -system.physmem_1.memoryStateTime::REF 94364660000 # Time in different power states +system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.369090 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states +system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26562494425 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory @@ -369,19 +368,19 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 23820996 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15588859 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 920395 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14518297 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 9504336 # Number of BTB hits +system.cpu0.branchPred.lookups 53057105 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.464538 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3840995 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33136 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 1356781 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 1203053 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 153728 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 48358 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,82 +411,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 66654 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 66654 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25108 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18968 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22578 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 460.137036 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2988.406264 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 42948 97.44% 97.44% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 855 1.94% 99.38% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 123 0.28% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 110 0.25% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 67255 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44076 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 16898 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11121.375311 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9757.603879 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6791.562531 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15594 92.28% 92.28% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1190 7.04% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 80 0.47% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 11 0.07% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 8 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 16898 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 90055870948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.547875 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.509370 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 89997968948 99.94% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 40556500 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7037000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4893500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1776500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1132500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1239500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1264500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 90055870948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5227 78.38% 78.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1442 21.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6669 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66654 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66654 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6669 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6669 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73323 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17666854 # DTB read hits -system.cpu0.dtb.read_misses 56136 # DTB read misses -system.cpu0.dtb.write_hits 14559303 # DTB write hits -system.cpu0.dtb.write_misses 10518 # DTB write misses +system.cpu0.dtb.read_hits 23647306 # DTB read hits +system.cpu0.dtb.read_misses 56401 # DTB read misses +system.cpu0.dtb.write_hits 17573284 # DTB write hits +system.cpu0.dtb.write_misses 10854 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3504 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2262 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 861 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17722990 # DTB read accesses -system.cpu0.dtb.write_accesses 14569821 # DTB write accesses +system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23703707 # DTB read accesses +system.cpu0.dtb.write_accesses 17584138 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32226157 # DTB hits -system.cpu0.dtb.misses 66654 # DTB misses -system.cpu0.dtb.accesses 32292811 # DTB accesses +system.cpu0.dtb.hits 41220590 # DTB hits +system.cpu0.dtb.misses 67255 # DTB misses +system.cpu0.dtb.accesses 41287845 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -517,58 +518,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10841 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10841 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3909 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5864 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1068 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 421.927760 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2234.177799 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9414 96.33% 96.33% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 108 1.11% 99.08% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 59 0.60% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 12 0.12% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12199.451303 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11419.234768 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4654.618910 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 570 15.64% 15.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2859 78.44% 94.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 148 4.06% 98.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.31% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 22 0.60% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 10944 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3645 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21336382212 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.847765 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.359386 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3249113500 15.23% 15.23% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 18086389212 84.77% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 793000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 86500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21336382212 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2247 87.19% 87.19% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 330 12.81% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2577 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10841 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10841 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13418 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37363257 # ITB inst hits -system.cpu0.itb.inst_misses 10841 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72708872 # ITB inst hits +system.cpu0.itb.inst_misses 10944 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -577,1022 +575,1029 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2348 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2345 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37374098 # ITB inst accesses -system.cpu0.itb.hits 37363257 # DTB hits -system.cpu0.itb.misses 10841 # DTB misses -system.cpu0.itb.accesses 37374098 # DTB accesses -system.cpu0.numCycles 130634754 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses +system.cpu0.itb.hits 72708872 # DTB hits +system.cpu0.itb.misses 10944 # DTB misses +system.cpu0.itb.accesses 72719816 # DTB accesses +system.cpu0.numCycles 202299816 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18759180 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 111594210 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 23820996 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14548384 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 105958075 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2723782 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 147803 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 403538 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 420731 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 91570 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37362977 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 256682 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5313 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 127200199 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.057439 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.258294 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 65301995 51.34% 51.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21243041 16.70% 68.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8702131 6.84% 74.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 31953032 25.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 127200199 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.182348 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.854246 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19580299 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 60730761 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 40895062 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4960019 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1034058 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3027631 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 331959 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 109730420 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3757258 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1034058 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25213970 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12473804 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 37385885 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40084231 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11008251 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 104776923 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1005898 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1454281 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 163264 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 59868 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6802738 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 108917617 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 478329249 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 119800886 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9453 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 97884799 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11032807 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1224750 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1083467 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12359769 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18590109 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16025944 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1692928 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2223672 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 101900058 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1687234 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100089682 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 451563 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8991464 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21250511 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 118873 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 127200199 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.786867 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.029325 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 634615161 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21721412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 71273767 56.03% 56.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23216726 18.25% 74.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22358125 17.58% 91.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9249672 7.27% 99.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1101855 0.87% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 54 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 127200199 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9294441 40.55% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 68 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5565368 24.28% 64.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8061478 35.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66026932 65.97% 65.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 92216 0.09% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8071 0.01% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18353253 18.34% 84.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15606936 15.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100089682 # Type of FU issued -system.cpu0.iq.rate 0.766180 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 22921355 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229008 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 350720067 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 112586232 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98062666 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32413 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11362 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9718 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 122987773 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20991 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 362703 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued +system.cpu0.iq.rate 0.656236 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1887830 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18911 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 876012 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 109448 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 364606 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1034058 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1622257 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 187065 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 103740401 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18590109 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16025944 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 873149 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28190 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 135133 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18911 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 251727 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 397563 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 649290 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99070135 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17913102 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 953014 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 261904 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 660097 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 153109 # number of nop insts executed -system.cpu0.iew.exec_refs 33359413 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16770669 # Number of branches executed -system.cpu0.iew.exec_stores 15446311 # Number of stores executed -system.cpu0.iew.exec_rate 0.758375 # Inst execution rate -system.cpu0.iew.wb_sent 98522156 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98072384 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51087973 # num instructions producing a value -system.cpu0.iew.wb_consumers 84406715 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.750737 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605260 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 7992419 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1568361 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 592562 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 125525573 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.754570 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.472389 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152457 # number of nop insts executed +system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25556056 # Number of branches executed +system.cpu0.iew.exec_stores 18461073 # Number of stores executed +system.cpu0.iew.exec_rate 0.651133 # Inst execution rate +system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 65950850 # num instructions producing a value +system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 81342054 64.80% 64.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24610935 19.61% 84.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8228457 6.56% 90.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3212332 2.56% 93.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3423017 2.73% 96.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1492381 1.19% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1160319 0.92% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 551485 0.44% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1504593 1.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 125525573 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78721743 # Number of instructions committed -system.cpu0.commit.committedOps 94717871 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 103938440 # Number of instructions committed +system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31852210 # Number of memory references committed -system.cpu0.commit.loads 16702278 # Number of loads committed -system.cpu0.commit.membars 645830 # Number of memory barriers committed -system.cpu0.commit.branches 16170329 # Number of branches committed +system.cpu0.commit.refs 40826228 # Number of memory references committed +system.cpu0.commit.loads 22662629 # Number of loads committed +system.cpu0.commit.membars 647252 # Number of memory barriers committed +system.cpu0.commit.branches 24954847 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81695650 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1925626 # Number of function calls committed. +system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4835454 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62767692 66.27% 66.27% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 89898 0.09% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.36% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8071 0.01% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.37% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16702278 17.63% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15149932 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 94717871 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1504593 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 222549197 # The number of ROB reads -system.cpu0.rob.rob_writes 207085893 # The number of ROB writes -system.cpu0.timesIdled 123342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3434555 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5521267593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78599691 # Number of Instructions Simulated -system.cpu0.committedOps 94595819 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.662026 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.662026 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.601675 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.601675 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110021691 # number of integer regfile reads -system.cpu0.int_regfile_writes 59386115 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8176 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 306287204 # The number of ROB reads +system.cpu0.rob.rob_writes 273994781 # The number of ROB writes +system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 103816388 # Number of Instructions Simulated +system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads +system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 349047979 # number of cc regfile reads -system.cpu0.cc_regfile_writes 40883845 # number of cc regfile writes -system.cpu0.misc_regfile_reads 177564457 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1222085 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 709600 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.965510 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28702051 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 710112 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.419048 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes +system.cpu0.misc_regfile_reads 274171027 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 709828 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.965510 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976495 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.976495 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63247390 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63247390 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15498209 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15498209 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11982969 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11982969 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307264 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307264 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 362251 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 362251 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360359 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 360359 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27481178 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27481178 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27788442 # number of overall hits -system.cpu0.dcache.overall_hits::total 27788442 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 646938 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 646938 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1889976 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1889976 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147980 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147980 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25182 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25182 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20295 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20295 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2536914 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2536914 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2684894 # number of overall misses -system.cpu0.dcache.overall_misses::total 2684894 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8613079000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8613079000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29673912872 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29673912872 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399362500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 399362500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 493278500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 493278500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 493500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 493500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38286991872 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38286991872 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38286991872 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38286991872 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16145147 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16145147 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13872945 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13872945 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 455244 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 455244 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387433 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387433 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 380654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 380654 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30018092 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30018092 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30473336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30473336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040070 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.040070 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136235 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136235 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325056 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325056 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064997 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064997 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084513 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084513 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088106 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088106 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13313.608105 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13313.608105 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15700.682375 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15700.682375 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15859.046144 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15859.046144 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24305.420054 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24305.420054 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits +system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses +system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15091.954978 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15091.954978 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14260.150260 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14260.150260 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1062 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4223116 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 202030 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.600000 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.903410 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 709603 # number of writebacks -system.cpu0.dcache.writebacks::total 709603 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260771 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 260771 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1564893 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1564893 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1825664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1825664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1825664 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1825664 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 386167 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386167 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325083 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325083 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102058 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102058 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6614 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6614 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20295 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20295 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 813308 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813308 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20340 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39373 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4553087000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4553087000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6070046902 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6070046902 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1659761500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1659761500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103454000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103454000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 472996500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 472996500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10623133902 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10623133902 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12282895402 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12282895402 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534665000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534665000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534665000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534665000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023918 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023918 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023433 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023433 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224183 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224183 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017071 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053316 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053316 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023694 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023694 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026689 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026689 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11790.461122 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11790.461122 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18672.298773 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18672.298773 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16262.924024 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16262.924024 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15641.669187 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15641.669187 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23306.060606 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23306.060606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15200.863572 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15200.863572 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14363.192642 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14363.192642 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks +system.cpu0.dcache.writebacks::total 709828 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14935.864889 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14935.864889 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15102.390979 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15102.390979 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222943.215339 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222943.215339 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115171.945242 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115171.945242 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1244973 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762786 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36061117 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1245485 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.953474 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6512698000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762786 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1253795 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 75964361 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 75964361 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36061117 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36061117 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36061117 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36061117 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36061117 # number of overall hits -system.cpu0.icache.overall_hits::total 36061117 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1298298 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1298298 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1298298 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1298298 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1298298 # number of overall misses -system.cpu0.icache.overall_misses::total 1298298 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13095750432 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13095750432 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13095750432 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13095750432 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13095750432 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13095750432 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37359415 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37359415 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37359415 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37359415 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37359415 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37359415 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034752 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034752 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034752 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034752 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034752 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034752 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10086.860206 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10086.860206 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10086.860206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10086.860206 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10086.860206 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1564537 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 822 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 111550 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.025433 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 74.727273 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1244973 # number of writebacks -system.cpu0.icache.writebacks::total 1244973 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52766 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 52766 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 52766 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 52766 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 52766 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 52766 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1245532 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1245532 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1245532 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1245532 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1245532 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1245532 # number of overall MSHR misses +system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits +system.cpu0.icache.overall_hits::total 71396857 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses +system.cpu0.icache.overall_misses::total 1308156 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 112621 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.086662 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1253795 # number of writebacks +system.cpu0.icache.writebacks::total 1253795 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53805 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 53805 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 53805 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 53805 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 53805 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 53805 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1254351 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1254351 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1254351 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1254351 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1254351 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1254351 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11887458427 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11887458427 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11887458427 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11887458427 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11887458427 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11887458427 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11994065954 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11994065954 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11994065954 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033339 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033339 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033339 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9544.081105 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9544.081105 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9544.081105 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836444 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1838932 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2249 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237260 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 275777 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16077.094616 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3264993 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 291873 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.186348 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 276743 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14642.260262 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 14.030425 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.082237 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1420.721692 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.893693 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000856 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086714 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981268 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15073 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 282 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 477 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4659 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6956 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2859 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919983 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66024498 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66024498 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55983 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13286 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 69269 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 482066 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 482066 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1441412 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1441412 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221318 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221318 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1193309 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1193309 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398313 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 398313 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55983 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13286 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1193309 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 619631 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1882209 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55983 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13286 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1193309 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 619631 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1882209 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 409 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 145 # number of ReadReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221301 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 221301 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1201423 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1201423 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses -system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses -system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55455 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55455 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20295 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20295 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48487 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48487 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52186 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 52186 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96414 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 96414 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 409 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 145 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 52186 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144901 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 197641 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 409 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 145 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 52186 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144901 # number of overall misses -system.cpu0.l2cache.overall_misses::total 197641 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11428500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3458500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 14887000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 116593500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 116593500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 25461000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 25461000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 459500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 459500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2707524000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2707524000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2738746000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2738746000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2927576997 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2927576997 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11428500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3458500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2738746000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5635100997 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8388733997 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11428500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3458500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2738746000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5635100997 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8388733997 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 56392 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13431 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 69823 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 482067 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 482067 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1441412 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1441412 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55456 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55456 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20295 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20295 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269805 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269805 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1245495 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1245495 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 494727 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 494727 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 56392 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13431 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1245495 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 764532 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2079850 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 56392 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13431 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1245495 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 764532 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2079850 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010796 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.007934 # miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47807 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 47807 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 52895 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 52895 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96473 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 96473 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 413 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 141 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 52895 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144280 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 197729 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 413 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 141 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 52895 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144280 # number of overall misses +system.cpu0.l2cache.overall_misses::total 197729 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11587500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3409000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 14996500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 108889500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 108889500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23948500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23948500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 220499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 220499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2771311500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2771311500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2784395500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2784395500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2944676496 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2944676496 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11587500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3409000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2784395500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5715987996 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 8515379996 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11587500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3409000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2784395500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5715987996 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 8515379996 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 55897 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 13384 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 69281 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481730 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 481730 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1450652 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1450652 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54994 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54994 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20107 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20107 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269108 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269108 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1254318 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1254318 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 495287 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 495287 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 55897 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 13384 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1254318 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 764395 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2087994 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 55897 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 13384 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1254318 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 764395 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2087994 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.010535 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.007996 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999964 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999964 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.179711 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179711 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041900 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041900 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194883 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194883 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010796 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041900 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189529 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.095027 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007253 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010796 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041900 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189529 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.095027 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23851.724138 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26871.841155 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2102.488504 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2102.488504 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1254.545455 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1254.545455 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55840.204591 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55840.204591 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52480.473690 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52480.473690 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30364.646182 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30364.646182 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 42444.300510 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27942.542787 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23851.724138 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52480.473690 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38889.317513 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 42444.300510 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.177650 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.177650 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042170 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042170 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.194782 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.194782 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.010535 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042170 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.188751 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.094698 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007389 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.010535 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042170 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.188751 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.094698 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24177.304965 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27069.494585 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1980.097105 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1980.097105 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1191.052867 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1191.052867 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 220499 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 220499 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57968.738888 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57968.738888 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 52640.051045 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 52640.051045 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 30523.322546 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 30523.322546 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 43065.913427 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28056.900726 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24177.304965 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 52640.051045 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39617.327391 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 43065.913427 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.666667 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10565 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 229088 # number of writebacks -system.cpu0.l2cache.writebacks::total 229088 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5680 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5680 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 39 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 39 # number of ReadCleanReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 771 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 771 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 39 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6451 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6490 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 39 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6451 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6490 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 409 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 145 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 255939 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55455 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55455 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20295 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20295 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42807 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42807 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52147 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52147 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95643 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95643 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 409 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 145 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52147 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138450 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 191151 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 409 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 145 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52147 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138450 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 255939 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 447090 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10266 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 229575 # number of writebacks +system.cpu0.l2cache.writebacks::total 229575 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5846 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 5846 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 35 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 35 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 765 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 765 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 35 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6611 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6647 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 35 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6611 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6647 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 412 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 141 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 553 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 257570 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54992 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54992 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 20107 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 20107 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41961 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41961 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 52860 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 52860 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 95708 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 95708 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 412 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 141 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 52860 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137669 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 191082 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 412 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 141 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 52860 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137669 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 257570 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 448652 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23343 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19033 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 34774 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42376 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2588500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11563000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15061119493 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1081830000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1081830000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 319630999 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 319630999 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 381500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 381500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1771002000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1771002000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2424780500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2424780500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2310424997 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2310424997 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2588500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2424780500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4081426997 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 6517770497 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8974500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2588500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2424780500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4081426997 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15061119493 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21578889990 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 63224 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2563000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11669500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15404483231 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067197500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067197500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 312794500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 312794500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 178499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 178499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1799957000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1799957000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2466178500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2466178500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2327314996 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2327314996 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2563000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2466178500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4127271996 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6605119996 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9106500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2563000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2466178500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4127271996 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15404483231 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 22009603227 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4371667500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4618288500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366568000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613189000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4371667500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4618288500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007934 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses -system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158659 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158659 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041868 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193325 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193325 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091906 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007253 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010796 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041868 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181091 # mshr miss rate for overall accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214963 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20871.841155 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58846.520042 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19508.249932 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19508.249932 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15749.248534 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15749.248534 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41371.784988 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41371.784988 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46498.945289 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24156.760003 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24156.760003 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34097.496205 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21942.542787 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17851.724138 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46498.945289 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29479.429375 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58846.520042 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48265.203852 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214929.572271 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197844.685773 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111032.115917 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108983.587408 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4059553 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2049525 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31130 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 322631 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318742 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3889 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 102054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1891052 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 711408 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1472505 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 201922 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 326386 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87454 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42857 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113442 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288333 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1245532 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576445 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3297 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3742005 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2570285 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29068 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119436 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6460794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 159437936 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98528220 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53724 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 225568 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 258245448 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1026066 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3122672 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120692 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.329569 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2749681 88.06% 88.06% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 369102 11.82% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3889 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3122672 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4044815993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114413841 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1871838919 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1215906771 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15648976 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63082921 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 34009026 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11598982 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 286954 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18822923 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 6035110 # Number of BTB hits +system.cpu1.branchPred.lookups 4689327 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 32.062555 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12529712 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7339 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 9024222 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 8987643 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 36579 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 11117 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1622,93 +1627,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 22019 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 22019 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8988 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5922 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7109 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14910 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 597.183099 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3274.563107 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 14271 95.71% 95.71% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 175 1.17% 96.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 226 1.52% 98.40% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.65% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 36 0.24% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 18 0.12% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 9 0.06% 99.48% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 63 0.42% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 6 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 3 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14910 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5586 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11231.919083 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9899.070869 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6145.006909 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1859 33.28% 33.28% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3110 55.67% 88.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 395 7.07% 96.03% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 162 2.90% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 30 0.54% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 21410 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5586 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72596800264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.178979 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.387926 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 59651088264 82.17% 82.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 12923549000 17.80% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 13278500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 4124000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1159000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 892500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 1267000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 399000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 261000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 175000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 102500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 47000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 179500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 63000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 38500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 176500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72596800264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1935 74.77% 74.77% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 653 25.23% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22019 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22019 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24607 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10217146 # DTB read hits -system.cpu1.dtb.read_misses 19031 # DTB read misses -system.cpu1.dtb.write_hits 6545704 # DTB write hits -system.cpu1.dtb.write_misses 2988 # DTB write misses +system.cpu1.dtb.read_hits 4195760 # DTB read hits +system.cpu1.dtb.read_misses 18440 # DTB read misses +system.cpu1.dtb.write_hits 3493575 # DTB write hits +system.cpu1.dtb.write_misses 2970 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 49 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 375 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2051 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 389 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10236177 # DTB read accesses -system.cpu1.dtb.write_accesses 6548692 # DTB write accesses +system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4214200 # DTB read accesses +system.cpu1.dtb.write_accesses 3496545 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16762850 # DTB hits -system.cpu1.dtb.misses 22019 # DTB misses -system.cpu1.dtb.accesses 16784869 # DTB accesses +system.cpu1.dtb.hits 7689335 # DTB hits +system.cpu1.dtb.misses 21410 # DTB misses +system.cpu1.dtb.accesses 7710745 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1738,58 +1737,57 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6065 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6065 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2849 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2599 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walks 5994 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 300.018355 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2054.443929 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 5317 97.60% 97.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.05% 98.64% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 30 0.55% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 22 0.40% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 8 0.15% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1777 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11882.104671 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10854.352895 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5876.427895 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 298 16.77% 16.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1356 76.31% 93.08% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 64 3.60% 96.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.41% 98.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 23 1.29% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 4 0.23% 99.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 3 0.17% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.17% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1777 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16742440916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.881191 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.323702 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1989886764 11.89% 11.89% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14751845152 88.11% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 691000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16742440916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 988 85.17% 85.17% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 172 14.83% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1160 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6065 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6065 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1160 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1160 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7225 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43720811 # ITB inst hits -system.cpu1.itb.inst_misses 6065 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8253439 # ITB inst hits +system.cpu1.itb.inst_misses 5994 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1798,887 +1796,887 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1192 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1194 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 560 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43726876 # ITB inst accesses -system.cpu1.itb.hits 43720811 # DTB hits -system.cpu1.itb.misses 6065 # DTB misses -system.cpu1.itb.accesses 43726876 # DTB accesses -system.cpu1.numCycles 106544770 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses +system.cpu1.itb.hits 8253439 # DTB hits +system.cpu1.itb.misses 5994 # DTB misses +system.cpu1.itb.accesses 8259433 # DTB accesses +system.cpu1.numCycles 34887121 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10285169 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 109329590 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 34009026 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27552465 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 93003678 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3760962 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 80448 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 30144 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 178688 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 297988 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23992 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43719656 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 111494 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2187 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105780588 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.280193 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339076 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 48754447 46.09% 46.09% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14049982 13.28% 59.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7558912 7.15% 66.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35417247 33.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105780588 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.319199 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.026138 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13239589 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62906745 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26778529 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1104926 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1750799 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 750846 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 132411 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 68206477 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1115402 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1750799 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17653779 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2374666 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57902702 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23447751 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2650891 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55293666 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 220143 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 265669 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37332 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18647 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1622767 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 55225885 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 261143833 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58792741 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1698 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52650074 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2575811 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1881943 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1808403 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13140602 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10477180 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6893389 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 629902 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 660425 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54420167 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 587049 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 54175023 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 95968 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3662766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5235414 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 44205 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105780588 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.512145 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.849831 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 103654423 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4727165 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72358023 68.40% 68.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16614078 15.71% 84.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13151335 12.43% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3370344 3.19% 99.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 286797 0.27% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 11 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105780588 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2941757 45.24% 45.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 670 0.01% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1685952 25.93% 71.19% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1873492 28.81% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36944686 68.20% 68.20% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46486 0.09% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3329 0.01% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.29% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10429510 19.25% 87.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6750946 12.46% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 54175023 # Type of FU issued -system.cpu1.iq.rate 0.508472 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6501871 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120016 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 220722500 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58678222 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 52198206 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5973 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2102 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued +system.cpu1.iq.rate 0.609164 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60672989 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3839 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 91219 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 444760 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 748 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10369 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 281379 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52226 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 78419 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1750799 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 547306 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 107318 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 55048106 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10477180 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6893389 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 299581 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 8072 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 92519 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10369 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45476 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 122774 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 168250 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53925594 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10330118 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 227431 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40890 # number of nop insts executed -system.cpu1.iew.exec_refs 17028825 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11888375 # Number of branches executed -system.cpu1.iew.exec_stores 6698707 # Number of stores executed -system.cpu1.iew.exec_rate 0.506131 # Inst execution rate -system.cpu1.iew.wb_sent 53782194 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 52199995 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25393405 # num instructions producing a value -system.cpu1.iew.wb_consumers 38775074 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.489935 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.654890 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 3417074 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 542844 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 157272 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103878319 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.494591 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.150147 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41057 # number of nop insts executed +system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3060021 # Number of branches executed +system.cpu1.iew.exec_stores 3625381 # Number of stores executed +system.cpu1.iew.exec_rate 0.602533 # Inst execution rate +system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10424214 # num instructions producing a value +system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77963106 75.05% 75.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14542376 14.00% 89.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6113605 5.89% 94.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 710011 0.68% 95.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1999110 1.92% 97.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1749013 1.68% 99.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 272868 0.26% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 126868 0.12% 99.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 401362 0.39% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103878319 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41730387 # Number of instructions committed -system.cpu1.commit.committedOps 51377304 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16334743 # Number of instructions committed +system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16644430 # Number of memory references committed -system.cpu1.commit.loads 10032420 # Number of loads committed -system.cpu1.commit.membars 210881 # Number of memory barriers committed -system.cpu1.commit.branches 11730295 # Number of branches committed +system.cpu1.commit.refs 7578069 # Number of memory references committed +system.cpu1.commit.loads 4036103 # Number of loads committed +system.cpu1.commit.membars 208295 # Number of memory barriers committed +system.cpu1.commit.branches 2905369 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46164743 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3380868 # Number of function calls committed. +system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions. +system.cpu1.commit.function_calls 462325 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34684147 67.51% 67.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45398 0.09% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3329 0.01% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.60% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10032420 19.53% 87.13% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6612010 12.87% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 51377304 # Class of committed instruction -system.cpu1.commit.bw_lim_events 401362 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 138158228 # The number of ROB reads -system.cpu1.rob.rob_writes 111482281 # The number of ROB writes -system.cpu1.timesIdled 55620 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 764182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5544797786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41697532 # Number of Instructions Simulated -system.cpu1.committedOps 51344449 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.555182 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.555182 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.391362 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.391362 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56568285 # number of integer regfile reads -system.cpu1.int_regfile_writes 35909809 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1388 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction +system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54190677 # The number of ROB reads +system.cpu1.rob.rob_writes 44052640 # The number of ROB writes +system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16301888 # Number of Instructions Simulated +system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads +system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 192177585 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15728126 # number of cc regfile writes -system.cpu1.misc_regfile_reads 146901400 # number of misc regfile reads -system.cpu1.misc_regfile_writes 390692 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 191412 # number of replacements -system.cpu1.dcache.tags.tagsinuse 467.958660 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15830019 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191751 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.555079 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89229031500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.958660 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913982 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.913982 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33166441 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33166441 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9618480 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9618480 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5953541 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5953541 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50151 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50151 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79497 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79497 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71560 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71560 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15572021 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15572021 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15622172 # number of overall hits -system.cpu1.dcache.overall_hits::total 15622172 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 219751 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 219751 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 400027 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 400027 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30362 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30362 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18466 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18466 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23631 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23631 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 619778 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 619778 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 650140 # number of overall misses -system.cpu1.dcache.overall_misses::total 650140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3494026000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3494026000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9769416956 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9769416956 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360558000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 360558000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 577732000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 577732000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 853500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 853500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13263442956 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13263442956 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13263442956 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13263442956 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9838231 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9838231 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6353568 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6353568 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80513 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80513 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97963 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97963 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95191 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95191 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16191799 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16191799 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16272312 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16272312 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022336 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022336 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062961 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.062961 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377107 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377107 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188500 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188500 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248248 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248248 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038277 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038277 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039954 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.039954 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15899.932196 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15899.932196 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24421.893912 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 24421.893912 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19525.506336 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19525.506336 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24448.055520 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24448.055520 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes +system.cpu1.misc_regfile_reads 50047969 # number of misc regfile reads +system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 189214 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits +system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses +system.cpu1.dcache.overall_misses::total 646053 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21400.312622 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21400.312622 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20400.902815 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20400.902815 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1422803 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 40164 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.633333 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35.424833 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 191413 # number of writebacks -system.cpu1.dcache.writebacks::total 191413 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80045 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 80045 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309351 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 309351 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13126 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 389396 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 389396 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 389396 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 389396 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139706 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139706 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90676 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90676 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28955 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28955 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5340 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5340 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23631 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23631 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230382 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259337 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259337 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14528 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26392 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1929657000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1929657000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2407624467 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2407624467 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488405000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488405000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 554116000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 554116000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 838500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 838500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4337281467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4337281467 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4825686467 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4825686467 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2529035000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2529035000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2529035000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2529035000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014200 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014272 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359631 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359631 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054510 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054510 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248248 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248248 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014228 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014228 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015937 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015937 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13812.270053 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13812.270053 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26551.948333 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26551.948333 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16867.725781 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16867.725781 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17152.059925 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17152.059925 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23448.690280 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23448.690280 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22186.510871 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22186.510871 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21147.676667 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21147.676667 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 397 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1522509 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 39 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 40277 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10.179487 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.800953 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 189214 # number of writebacks +system.cpu1.dcache.writebacks::total 189214 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79118 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79118 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 308913 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 308913 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13245 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13245 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 388031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 388031 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 388031 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 388031 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136805 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136805 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90967 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90967 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28906 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28906 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5365 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5365 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23458 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23458 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 227772 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 227772 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256678 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256678 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5513 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1918091000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1918091000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2479606465 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2479606465 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 495967500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 495967500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4893664965 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4893664965 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 441985000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 441985000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 441985000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 441985000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035564 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035564 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14020.620591 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14020.620591 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.307573 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.307573 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18826.477186 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18826.477186 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18607.782411 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18607.782411 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174080.052313 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174080.052313 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95825.818430 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95825.818430 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 601488 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.448304 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43094812 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 602000 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 71.586066 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79058224000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448304 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 585593 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 88040802 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 88040802 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43094812 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43094812 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43094812 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43094812 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43094812 # number of overall hits -system.cpu1.icache.overall_hits::total 43094812 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 624586 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 624586 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 624586 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 624586 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 624586 # number of overall misses -system.cpu1.icache.overall_misses::total 624586 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5619455793 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5619455793 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5619455793 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5619455793 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5619455793 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5619455793 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43719398 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43719398 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43719398 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43719398 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43719398 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43719398 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014286 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014286 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014286 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014286 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014286 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014286 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8997.088941 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8997.088941 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8997.088941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8997.088941 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8997.088941 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 497106 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 2 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41763 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.903024 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 601488 # number of writebacks -system.cpu1.icache.writebacks::total 601488 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22580 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22580 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22580 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22580 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22580 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22580 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 602006 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 602006 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 602006 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 602006 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 602006 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 602006 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits +system.cpu1.icache.overall_hits::total 7643805 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 608184 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 608184 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 608184 # number of overall misses +system.cpu1.icache.overall_misses::total 608184 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5475305711 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5475305711 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5475305711 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5475305711 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5475305711 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5475305711 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8251989 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks +system.cpu1.icache.writebacks::total 585593 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5157000587 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5157000587 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5157000587 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5157000587 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5157000587 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5157000587 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9463000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9463000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9463000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9463000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013770 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013770 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013770 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013770 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8566.360779 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8566.360779 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8566.360779 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92774.509804 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92774.509804 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92774.509804 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 196563 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 197115 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 493 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5018314097 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5018314097 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5018314097 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5018314097 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9229000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9229000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9229000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9229000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071027 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071027 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071027 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8561.995678 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59469 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47848 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15152.810983 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1369588 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62482 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 21.919721 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 51951 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14657.752176 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.247040 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.961226 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 482.850541 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.894638 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.970486 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 470.415625 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.902158 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000969 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029471 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.924854 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1015 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 873 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 127 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028712 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.932020 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13541 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 870 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 142 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 454 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8865 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4269 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.061951 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 27297276 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 27297276 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17323 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6382 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 23705 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 116494 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 116494 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 663845 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 663845 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27330 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27330 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 585501 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 585501 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 105069 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 105069 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17323 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6382 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 585501 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 132399 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 741605 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17323 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6382 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 585501 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 132399 # number of overall hits -system.cpu1.l2cache.overall_hits::total 741605 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 251 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 687 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29837 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29837 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23628 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23628 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34183 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34183 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16502 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 16502 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68911 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 68911 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 251 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 16502 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103094 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 120283 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 251 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 16502 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103094 # number of overall misses -system.cpu1.l2cache.overall_misses::total 120283 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9535000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5307000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 14842000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65279500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 65279500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 35645500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 35645500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 815499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 815499 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382048000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1382048000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 678918000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 678918000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1543279999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1543279999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9535000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5307000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 678918000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2925327999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3619087999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9535000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5307000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 678918000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2925327999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3619087999 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17759 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6633 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 24392 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 116494 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 116494 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 663845 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 663845 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29837 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29837 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23628 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23628 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61513 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61513 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 602003 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 602003 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 173980 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 173980 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17759 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6633 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 602003 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 235493 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 861888 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17759 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6633 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 602003 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 235493 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 861888 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037841 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.028165 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 115107 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 115107 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 647294 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 647294 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27150 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27150 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570057 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 570057 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101740 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 101740 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16755 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits +system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69320 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 69320 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 448 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 16047 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 103916 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 120654 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 448 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 16047 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 103916 # number of overall misses +system.cpu1.l2cache.overall_misses::total 120654 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9860500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5063000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 14923500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63584500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 63584500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34923000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34923000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1206498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1206498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1459821998 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1459821998 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658205000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658205000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1571289999 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1571289999 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9860500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5063000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658205000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3031111997 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 6472 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 23675 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 115107 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 115107 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 647294 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 647294 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29892 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29892 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23453 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23453 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61746 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61746 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 586104 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 586104 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171060 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 171060 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17203 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 6472 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 586104 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 232806 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 842585 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17203 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 6472 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 586104 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 232806 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 842585 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037546 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.029187 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555704 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555704 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027412 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027412 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.396086 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.396086 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037841 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027412 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.437779 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.139558 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024551 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037841 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027412 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.437779 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.139558 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21143.426295 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21604.075691 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2187.870764 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2187.870764 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1508.612663 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1508.612663 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 271833 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 271833 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40430.857444 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40430.857444 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41141.558599 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41141.558599 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22395.263441 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22395.263441 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30088.108868 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21869.266055 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21143.426295 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41141.558599 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28375.346761 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30088.108868 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560295 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560295 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027379 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027379 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405238 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405238 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037546 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027379 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.446363 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.143195 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026042 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037546 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027379 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.446363 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.143195 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20835.390947 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21596.960926 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2127.141041 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2127.141041 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1489.063233 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1489.063233 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 241299.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 241299.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42196.265406 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42196.265406 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 41017.324110 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 41017.324110 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22667.195600 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22667.195600 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 30701.348459 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22010.044643 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20835.390947 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41017.324110 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29168.867133 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 30701.348459 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25.666667 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 878 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 32705 # number of writebacks -system.cpu1.l2cache.writebacks::total 32705 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 447 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 447 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 9 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 70 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 70 # number of ReadSharedReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 517 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 526 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 517 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 526 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 436 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 251 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 25391 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29837 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29837 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23628 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23628 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33736 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33736 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16493 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16493 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68841 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68841 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 436 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 251 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16493 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102577 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 119757 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 436 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 251 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16493 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102577 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25391 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 145148 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 821 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 37285 # number of writebacks +system.cpu1.l2cache.writebacks::total 37285 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 74 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 74 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 647 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 651 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 647 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 651 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 448 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 691 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 27204 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29892 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29892 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23453 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23453 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34023 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34023 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16043 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16043 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69246 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69246 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 448 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16043 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103269 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 120003 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 448 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16043 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103269 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27204 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 147207 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14528 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14630 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11864 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3180 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26392 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26494 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3801000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10720000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1003077137 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 504358500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 504358500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 376609000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 376609000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 725499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 725499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1128947000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1128947000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 579803500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 579803500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1128190999 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1128190999 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3801000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 579803500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2257137999 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2847661499 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6919000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3801000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 579803500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2257137999 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1003077137 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3850738636 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8698000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412762500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2421460500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8698000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412762500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2421460500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028165 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5615 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3605000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10777500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1221222561 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 499462500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 499462500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 372532500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 372532500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1056498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1056498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1184971500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1184971500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 561881000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 561881000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1153728499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1153728499 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3605000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 561881000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2338699999 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2911358499 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7172500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3605000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 561881000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2338699999 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1221222561 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4132581060 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8464000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417313000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 425777000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8464000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417313000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 425777000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029187 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2687,117 +2685,117 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548437 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548437 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027397 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.395683 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.395683 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138947 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024551 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037841 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027397 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435584 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551015 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551015 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027372 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404805 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404805 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142422 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026042 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.037546 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027372 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443584 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168407 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15604.075691 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39505.223780 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16903.793947 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16903.793947 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15939.097681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15939.097681 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 241833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 241833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33464.162912 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33464.162912 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35154.520099 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16388.358667 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16388.358667 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23778.664287 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15869.266055 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15143.426295 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35154.520099 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22004.328446 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39505.223780 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26529.739549 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166076.713932 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165513.362953 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 85274.509804 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91420.222037 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91396.561486 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1693819 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 856333 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 183235 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 181854 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1381 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 43509 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 857970 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 150213 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 676407 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 108999 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41945 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86317 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68814 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66024 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 602006 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 255355 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 206 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1805701 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 897982 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14680 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38591 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2756954 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 77025056 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30176714 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26532 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71036 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 107299338 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 403916 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1269906 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.163115 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.372403 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174709 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15596.960926 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44891.286612 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16708.902047 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16708.902047 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15884.215239 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15884.215239 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 211299.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 211299.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34828.542457 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34828.542457 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35023.437013 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 408149 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1064146 83.80% 83.80% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 204379 16.09% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1381 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1269906 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1668457495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80964876 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 903243234 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 401728937 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8056980 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20851461 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31007 # Transaction distribution -system.iobus.trans_dist::ReadResp 31007 # Transaction distribution +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution system.iobus.trans_dist::WriteResp 59421 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) @@ -2820,9 +2818,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180856 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2843,34 +2841,34 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484002 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40388000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 330000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 574500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) @@ -2878,56 +2876,56 @@ system.iobus.reqLayer19.occupancy 2500 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6116000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33795000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187654365 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36766000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36453 # number of replacements -system.iocache.tags.tagsinuse 14.555427 # Cycle average of tags in use +system.iocache.tags.replacements 36458 # number of replacements +system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255133996000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555427 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909714 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909714 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328239 # Number of tag accesses -system.iocache.tags.data_accesses 328239 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses -system.iocache.ReadReq_misses::total 247 # number of ReadReq misses +system.iocache.tags.tag_accesses 328284 # Number of tag accesses +system.iocache.tags.data_accesses 328284 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36471 # number of demand (read+write) misses -system.iocache.demand_misses::total 36471 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36471 # number of overall misses -system.iocache.overall_misses::total 36471 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32034877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32034877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4302643488 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4302643488 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4334678365 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4334678365 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4334678365 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4334678365 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses +system.iocache.demand_misses::total 36476 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36476 # number of overall misses +system.iocache.overall_misses::total 36476 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36471 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36471 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36471 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36471 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2936,14 +2934,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129695.858300 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129695.858300 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118778.806537 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118778.806537 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118852.742316 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118852.742316 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118852.742316 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -2952,22 +2950,22 @@ system.iocache.avg_blocked_cycles::no_mshrs 3 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 247 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 247 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36471 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36471 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36471 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36471 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19684877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19684877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489128459 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2489128459 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2508813336 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2508813336 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2508813336 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2508813336 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36476 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2976,599 +2974,598 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79695.858300 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79695.858300 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68714.897830 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68714.897830 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68789.266431 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68789.266431 # average overall mshr miss latency -system.l2c.tags.replacements 126939 # number of replacements -system.l2c.tags.tagsinuse 63214.740893 # Cycle average of tags in use -system.l2c.tags.total_refs 439035 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 190800 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.301022 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency +system.l2c.tags.replacements 132778 # number of replacements +system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use +system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13659.794415 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.383881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.061858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8032.623601 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2877.626716 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34705.867730 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 3.664427 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910014 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1967.326736 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 460.362743 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1490.118772 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.208432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.122568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043909 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.529570 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000056 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.030019 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964580 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29285 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34558 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5757 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6476 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27436 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.446854 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000275 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.527313 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6030021 # Number of tag accesses -system.l2c.tags.data_accesses 6030021 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 261794 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 261794 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32586 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2322 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34908 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2057 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1031 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3088 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3923 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1723 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5646 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 188 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 73 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 32795 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 46613 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 68 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 36 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 13556 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9028 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5103 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 153946 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 188 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 73 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 32795 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 50536 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 46486 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 13556 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10751 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5103 # number of demand (read+write) hits -system.l2c.demand_hits::total 159592 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 188 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 73 # number of overall hits -system.l2c.overall_hits::cpu0.inst 32795 # number of overall hits -system.l2c.overall_hits::cpu0.data 50536 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46486 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13556 # number of overall hits -system.l2c.overall_hits::cpu1.data 10751 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5103 # number of overall hits -system.l2c.overall_hits::total 159592 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9262 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3049 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12311 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 797 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1327 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2124 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11181 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8169 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19350 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6131058 # Number of tag accesses +system.l2c.tags.data_accesses 6131058 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 155096 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 163 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 33190 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51018 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 46066 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 73 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 13227 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 11214 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5456 # number of demand (read+write) hits +system.l2c.demand_hits::total 160511 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 163 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits +system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits +system.l2c.overall_hits::cpu0.data 51018 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits +system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits +system.l2c.overall_hits::cpu1.data 11214 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits +system.l2c.overall_hits::total 160511 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1290 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1945 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11642 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8933 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 20575 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 27 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 19352 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9056 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 5 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 19670 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9220 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2936 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 955 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 170195 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2815 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1145 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 174280 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19352 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20237 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 19670 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20862 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9124 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) misses -system.l2c.demand_misses::total 189545 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2815 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10078 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) misses +system.l2c.demand_misses::total 194855 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 19352 # number of overall misses -system.l2c.overall_misses::cpu0.data 20237 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 131166 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 19670 # number of overall misses +system.l2c.overall_misses::cpu0.data 20862 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133244 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2936 # number of overall misses -system.l2c.overall_misses::cpu1.data 9124 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6696 # number of overall misses -system.l2c.overall_misses::total 189545 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 10685000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2955500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13640500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1570500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1260500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2831000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1150734500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 687988500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1838723000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2363000 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu1.inst 2815 # number of overall misses +system.l2c.overall_misses::cpu1.data 10078 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 8148 # number of overall misses +system.l2c.overall_misses::total 194855 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 8725000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2891500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11616500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1430000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1143000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2573000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1196035499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 747656500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1943691999 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2599000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 241000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1607400500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 824224000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 522500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 83500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 250906500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 89245500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 17878713282 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2363000 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1635002000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 838941000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 652000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 97500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 242297000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 106324000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 18502691507 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2599000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 241000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1607400500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1974958500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 522500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 250906500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 777234000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19717436282 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2363000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1635002000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2034976499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 652000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 97500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 242297000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 853980500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20446383506 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2599000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 241000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1607400500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1974958500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14216291987 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 522500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 250906500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 777234000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 887434795 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19717436282 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 261794 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 261794 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 41848 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5371 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 47219 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2854 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2358 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 5212 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15104 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9892 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24996 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 213 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 76 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 52147 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 55669 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177652 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 73 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 16492 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 9983 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11799 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 324141 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 213 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 52147 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 70773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177652 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 73 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 16492 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19875 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11799 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 349137 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 213 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 52147 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 70773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177652 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 73 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 16492 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19875 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11799 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 349137 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.221325 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.567678 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.260721 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.279257 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.562765 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.407521 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.740267 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.825819 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.774124 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.039474 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.371105 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162676 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.027027 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.178026 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.095663 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.525065 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.039474 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.371105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.285942 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.027027 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.178026 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.459069 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.542896 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.117371 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.039474 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.371105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.285942 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738331 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.068493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.027027 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.178026 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.459069 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.567506 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.542896 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1153.638523 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 969.334208 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1107.992852 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1970.514429 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 949.886963 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1332.862524 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102918.746087 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84219.427102 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 95024.444444 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 94520 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 1635002000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2034976499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14574955860 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 652000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 97500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 242297000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 853980500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1101582147 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20446383506 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 266860 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 266860 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 41414 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5457 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46871 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2664 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4887 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15678 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10312 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25990 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 190 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 52860 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 56202 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179310 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 30 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 16042 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 10980 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 13604 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 329376 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 52860 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 71880 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179310 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 30 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 16042 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 21292 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13604 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 355366 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 52860 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 71880 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179310 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 30 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 16042 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21292 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13604 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 355366 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.216931 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.507788 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.250795 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.245871 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.580297 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.397995 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.742569 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.866272 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.791651 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.038462 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372115 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164051 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.033333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.175477 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.104281 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.529122 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.038462 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.372115 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.033333 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.175477 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.473323 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.548322 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.142105 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.038462 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.372115 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.743093 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.087500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.033333 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.175477 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.473323 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.598941 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.548322 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 971.170971 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1043.486106 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 988.217780 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2183.206107 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 886.046512 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1322.879177 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102734.538653 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83696.014777 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 94468.626926 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 80333.333333 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83061.208144 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 91014.134276 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 85458.617166 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 93450.785340 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 105048.404959 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 83121.606507 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90991.431670 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 97500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86073.534636 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92859.388646 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 106166.464924 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 104025.093155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 94520 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 104931.274568 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96259.259259 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80333.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83061.208144 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 97591.466126 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 108383.971357 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85458.617166 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 85185.664182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132532.078106 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 104025.093155 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 838 # number of cycles access was blocked +system.l2c.overall_avg_miss_latency::cpu0.inst 83121.606507 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 97544.650513 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109385.457206 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93142.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 86073.534636 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 84737.100615 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 135196.630707 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 104931.274568 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 21 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 104.750000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 99614 # number of writebacks -system.l2c.writebacks::total 99614 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 7 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 3468 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 3468 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9262 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3049 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12311 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 797 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1327 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2124 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11181 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8169 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19350 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses +system.l2c.writebacks::writebacks 103743 # number of writebacks +system.l2c.writebacks::total 103743 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3708 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3708 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8984 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2771 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11755 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1290 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1945 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11642 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8933 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 20575 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19350 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9056 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 19662 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9220 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2929 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 955 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 170186 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2807 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1145 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 174264 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 19350 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20237 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 19662 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20862 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2929 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9124 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 189536 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2807 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10078 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 194839 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 19350 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20237 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 131166 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 19662 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20862 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133244 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2929 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9124 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6696 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 189536 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2807 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10078 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 8148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 194839 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3003 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 20340 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14525 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 37970 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19033 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11864 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30897 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 37951 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30885 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 39373 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26389 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 68867 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 221469500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 70279500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 291749000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20549499 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32977500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 53526999 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1038924500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 606298001 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1645222501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5510 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 68836 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213623000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63075000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 276698000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16864000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32149500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 49013500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1079614502 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 658325502 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1737940004 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 211000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1413871007 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 733663501 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 472500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 221234502 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 79695500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 16176437301 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1437895505 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 746740501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 582000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 87500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 213731003 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 94873501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 16759063028 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 211000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1413871007 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1772588001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 472500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 221234502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 685993501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17821659802 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2113000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1437895505 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1826355003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 582000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 87500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 213731003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 753199003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18497003032 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2329000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 211000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1413871007 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1772588001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12904628993 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 472500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 221234502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 685993501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 820473798 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17821659802 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1437895505 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1826355003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13242511370 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 582000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 87500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 213731003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 753199003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1020101648 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18497003032 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 192566500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4005508001 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6861000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2151256501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6356192002 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5794669001 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6627000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361914000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6355776501 # number of ReadReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 192566500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4005508001 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6861000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2151256501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6356192002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5794669001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6627000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 361914000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6355776501 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.221325 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.567678 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.260721 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.279257 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.562765 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.407521 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.740267 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.825819 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774124 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162676 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.095663 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.525037 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.542870 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.117371 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.039474 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371066 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.285942 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738331 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.068493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.027027 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.459069 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.567506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.542870 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23911.628158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 23050.016399 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23698.237349 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25783.562108 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24851.168048 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25201.035311 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92918.746087 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74219.366018 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 85024.418656 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.216931 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.507788 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.250795 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.245871 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.580297 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.397995 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.742569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866272 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.791651 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.164051 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.104281 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.529073 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.548277 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.142105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.038462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371964 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.743093 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.087500 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.033333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.174978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.473323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.598941 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.548277 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23778.161175 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22762.540599 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23538.749468 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25746.564885 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24922.093023 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25199.742931 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92734.453015 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73695.903056 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 84468.529964 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81014.079174 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83450.785340 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 95051.515994 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80991.377549 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82858.952838 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96170.540261 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73068.269096 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87591.441469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98383.948531 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75532.434961 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75185.609491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122531.929211 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94027.835356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196927.630334 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148107.160138 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167400.368765 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101732.354685 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 67264.705882 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81520.955739 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92296.629765 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 514606 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 294659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 567 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 37970 # Transaction distribution -system.membus.trans_dist::ReadResp 208402 # Transaction distribution -system.membus.trans_dist::WriteReq 30897 # Transaction distribution -system.membus.trans_dist::WriteResp 30897 # Transaction distribution -system.membus.trans_dist::WritebackDirty 135820 # Transaction distribution -system.membus.trans_dist::CleanEvict 15995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76425 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40810 # Transaction distribution +system.membus.trans_dist::ReadReq 37951 # Transaction distribution +system.membus.trans_dist::ReadResp 212466 # Transaction distribution +system.membus.trans_dist::WriteReq 30885 # Transaction distribution +system.membus.trans_dist::WriteResp 30885 # Transaction distribution +system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution +system.membus.trans_dist::CleanEvict 17155 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38865 # Transaction distribution -system.membus.trans_dist::ReadExResp 19252 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170433 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 40333 # Transaction distribution +system.membus.trans_dist::ReadExResp 20490 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13670 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 646867 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 768487 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 841426 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18547336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18737758 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21055902 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122883 # Total snoops (count) -system.membus.snoop_fanout::samples 431628 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011899 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108432 # Request fanout histogram +system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122014 # Total snoops (count) +system.membus.snoop_fanout::samples 435296 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 426492 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5136 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 431628 # Request fanout histogram -system.membus.reqLayer0.occupancy 81611500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 435296 # Request fanout histogram +system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11561000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 995379161 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1093943847 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1316877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3611,56 +3608,56 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1005681 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 545297 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 156423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20020 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 950 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 37973 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 482978 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30897 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30897 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 361408 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 120637 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 111235 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43898 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 155133 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 28 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50623 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50623 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 445008 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4567 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1196695 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 348487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1545182 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34087104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5287070 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39374174 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 380983 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 851193 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.382254 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.488230 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382843 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 526771 61.89% 61.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 323472 38.00% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 950 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 851193 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 876200249 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 348123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 630764010 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 246030993 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6a568c6cc..a08043e3c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116306 # Simulator instruction rate (inst/s) -host_op_rate 141069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2913147103 # Simulator tick rate (ticks/s) -host_mem_usage 578076 # Number of bytes of host memory used -host_seconds 972.44 # Real time elapsed on the host +host_inst_rate 70501 # Simulator instruction rate (inst/s) +host_op_rate 85511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1765850548 # Simulator tick rate (ticks/s) +host_mem_usage 578080 # Number of bytes of host memory used +host_seconds 1604.25 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -429,9 +429,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25410889 # DTB read hits +system.cpu.dtb.read_hits 25410890 # DTB read hits system.cpu.dtb.read_misses 62740 # DTB read misses -system.cpu.dtb.write_hits 19865162 # DTB write hits +system.cpu.dtb.write_hits 19865163 # DTB write hits system.cpu.dtb.write_misses 9628 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -442,12 +442,12 @@ system.cpu.dtb.align_faults 362 # Nu system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25473629 # DTB read accesses -system.cpu.dtb.write_accesses 19874790 # DTB write accesses +system.cpu.dtb.read_accesses 25473630 # DTB read accesses +system.cpu.dtb.write_accesses 19874791 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45276051 # DTB hits +system.cpu.dtb.hits 45276053 # DTB hits system.cpu.dtb.misses 72368 # DTB misses -system.cpu.dtb.accesses 45348419 # DTB accesses +system.cpu.dtb.accesses 45348421 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -551,7 +551,7 @@ system.cpu.itb.accesses 66008446 # DT system.cpu.numCycles 278423951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken @@ -565,21 +565,21 @@ system.cpu.fetch.IcacheWaitRetryStallCycles 188 # system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking @@ -589,7 +589,7 @@ system.cpu.decode.BranchMispred 467954 # Nu system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running @@ -620,14 +620,14 @@ system.cpu.iq.iqSquashedInstsIssued 260968 # Nu system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -636,7 +636,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available @@ -709,7 +709,7 @@ system.cpu.iq.FU_type_0::total 143038678 # Ty system.cpu.iq.rate 0.513744 # Inst issue rate system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads @@ -753,30 +753,30 @@ system.cpu.iew.exec_stores 20827406 # Nu system.cpu.iew.exec_rate 0.510511 # Inst execution rate system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63237138 # num instructions producing a value -system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value +system.cpu.iew.wb_producers 63237137 # num instructions producing a value +system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle system.cpu.commit.committedInsts 113255406 # Number of instructions committed system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -822,11 +822,11 @@ system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction -system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389119867 # The number of ROB reads +system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389119868 # The number of ROB reads system.cpu.rob.rob_writes 292294903 # The number of ROB writes system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 113100501 # Number of Instructions Simulated system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated @@ -834,19 +834,19 @@ system.cpu.cpi 2.461739 # CP system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155524958 # number of integer regfile reads +system.cpu.int_regfile_reads 155524954 # number of integer regfile reads system.cpu.int_regfile_writes 88488761 # number of integer regfile writes system.cpu.fp_regfile_reads 9529 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502156058 # number of cc regfile reads +system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads +system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy @@ -856,22 +856,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits -system.cpu.dcache.overall_hits::total 39152130 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits +system.cpu.dcache.overall_hits::total 39152132 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses @@ -898,20 +898,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 16738d5e3..42b6a0fb0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.823729 # Nu sim_ticks 2823728611500 # Number of ticks simulated final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263665 # Simulator instruction rate (inst/s) -host_op_rate 319829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6058824639 # Simulator tick rate (ticks/s) -host_mem_usage 584988 # Number of bytes of host memory used -host_seconds 466.05 # Real time elapsed on the host +host_inst_rate 192143 # Simulator instruction rate (inst/s) +host_op_rate 233071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4415299854 # Simulator tick rate (ticks/s) +host_mem_usage 584992 # Number of bytes of host memory used +host_seconds 639.53 # Real time elapsed on the host sim_insts 122881667 # Number of instructions simulated sim_ops 149056790 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -432,9 +432,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4099 system.cpu0.dtb.walker.walkRequestOrigin::total 9070 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12098970 # DTB read hits +system.cpu0.dtb.read_hits 12098971 # DTB read hits system.cpu0.dtb.read_misses 4249 # DTB read misses -system.cpu0.dtb.write_hits 9143698 # DTB write hits +system.cpu0.dtb.write_hits 9143699 # DTB write hits system.cpu0.dtb.write_misses 722 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA @@ -445,12 +445,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 830 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12103219 # DTB read accesses -system.cpu0.dtb.write_accesses 9144420 # DTB write accesses +system.cpu0.dtb.read_accesses 12103220 # DTB read accesses +system.cpu0.dtb.write_accesses 9144421 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21242668 # DTB hits +system.cpu0.dtb.hits 21242670 # DTB hits system.cpu0.dtb.misses 4971 # DTB misses -system.cpu0.dtb.accesses 21247639 # DTB accesses +system.cpu0.dtb.accesses 21247641 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -535,7 +535,7 @@ system.cpu0.num_conditional_control_insts 7357632 # n system.cpu0.num_int_insts 58995481 # number of integer instructions system.cpu0.num_fp_insts 4380 # number of float instructions system.cpu0.num_int_register_reads 108779991 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41129871 # number of times the integer registers were written +system.cpu0.num_int_register_writes 41129875 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written system.cpu0.num_cc_register_reads 204568240 # number of times the CC registers were read @@ -585,9 +585,9 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 68312506 # Class of executed instruction system.cpu0.dcache.tags.replacements 833701 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45908567 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 834213 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.032188 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.032191 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.062806 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.552141 # Average occupied blocks per requestor @@ -603,18 +603,18 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193086181 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193086181 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11466813 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu3.data 6693194 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25812081 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8805126 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::total 25812082 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8805127 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 2681872 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 3150720 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu3.data 4155645 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18793363 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18793364 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178315 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56771 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67457 # number of SoftPFReq hits @@ -630,16 +630,16 @@ system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76661 system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73616 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92634 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20271939 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 20271941 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 6285887 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu2.data 7198779 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu3.data 10848839 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44605444 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20450254 # number of overall hits +system.cpu0.dcache.demand_hits::total 44605446 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20450256 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 6342658 # number of overall hits system.cpu0.dcache.overall_hits::cpu2.data 7266236 # number of overall hits system.cpu0.dcache.overall_hits::cpu3.data 10934832 # number of overall hits -system.cpu0.dcache.overall_hits::total 44993980 # number of overall hits +system.cpu0.dcache.overall_hits::total 44993982 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170779 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 51895 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 83860 # number of ReadReq misses @@ -695,16 +695,16 @@ system.cpu0.dcache.overall_miss_latency::cpu1.data 2109020500 system.cpu0.dcache.overall_miss_latency::cpu2.data 6256851496 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu3.data 64471692312 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 72837564308 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637592 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11637593 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 3655910 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu2.data 4131919 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu3.data 6912790 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26338211 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917441 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26338212 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 8917442 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 2716710 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 3254660 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu3.data 5382372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20271183 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20271184 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232245 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76230 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86787 # number of SoftPFReq accesses(hits+misses) @@ -720,16 +720,16 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76661 system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73616 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92661 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460703 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20555033 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 20555035 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 6372620 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu2.data 7386579 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu3.data 12295162 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46609394 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20787278 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 46609396 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 20787280 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 6448850 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu2.data 7473366 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu3.data 12423880 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47133374 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 47133376 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014675 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014195 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020296 # miss rate for ReadReq accesses diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index a8fee84d0..8140fab33 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.804583 # Nu sim_ticks 2804582834000 # Number of ticks simulated final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128680 # Simulator instruction rate (inst/s) -host_op_rate 156182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3087037891 # Simulator tick rate (ticks/s) -host_mem_usage 586780 # Number of bytes of host memory used -host_seconds 908.50 # Real time elapsed on the host +host_inst_rate 77550 # Simulator instruction rate (inst/s) +host_op_rate 94124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1860425573 # Simulator tick rate (ticks/s) +host_mem_usage 586788 # Number of bytes of host memory used +host_seconds 1507.50 # Real time elapsed on the host sim_insts 116905819 # Number of instructions simulated sim_ops 141891765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -459,9 +459,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5107 system.cpu0.dtb.walker.walkRequestOrigin::total 64239 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13759363 # DTB read hits +system.cpu0.dtb.read_hits 13759364 # DTB read hits system.cpu0.dtb.read_misses 49716 # DTB read misses -system.cpu0.dtb.write_hits 10256386 # DTB write hits +system.cpu0.dtb.write_hits 10256387 # DTB write hits system.cpu0.dtb.write_misses 9416 # DTB write misses system.cpu0.dtb.flush_tlb 182 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA @@ -472,12 +472,12 @@ system.cpu0.dtb.align_faults 822 # Nu system.cpu0.dtb.prefetch_faults 1317 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13809079 # DTB read accesses -system.cpu0.dtb.write_accesses 10265802 # DTB write accesses +system.cpu0.dtb.read_accesses 13809080 # DTB read accesses +system.cpu0.dtb.write_accesses 10265803 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24015749 # DTB hits +system.cpu0.dtb.hits 24015751 # DTB hits system.cpu0.dtb.misses 59132 # DTB misses -system.cpu0.dtb.accesses 24074881 # DTB accesses +system.cpu0.dtb.accesses 24074883 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -584,7 +584,7 @@ system.cpu0.itb.accesses 19913313 # DT system.cpu0.numCycles 106457732 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39778101 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 39778104 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 102329331 # Number of instructions fetch has processed system.cpu0.fetch.Branches 26563319 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 19038002 # Number of branches that fetch has predicted taken @@ -599,11 +599,11 @@ system.cpu0.fetch.IcacheWaitRetryStallCycles 483 system.cpu0.fetch.CacheLines 19903626 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 349456 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 4039 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103827958 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 103827961 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::mean 1.185750 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::stdev 2.289369 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75543670 72.76% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75543673 72.76% 72.76% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::1 3812816 3.67% 76.43% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 2351525 2.26% 78.70% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::3 7978907 7.68% 86.38% # Number of instructions fetched each cycle (Total) @@ -615,10 +615,10 @@ system.cpu0.fetch.rateDist::8 4481059 4.32% 100.00% # Nu system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103827958 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 103827961 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.249520 # Number of branch fetches per cycle system.cpu0.fetch.rate 0.961220 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27448347 # Number of cycles decode is idle +system.cpu0.decode.IdleCycles 27448350 # Number of cycles decode is idle system.cpu0.decode.BlockedCycles 58255743 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 15281337 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 1431455 # Number of cycles decode is unblocking @@ -628,7 +628,7 @@ system.cpu0.decode.BranchMispred 143809 # Nu system.cpu0.decode.DecodedInsts 84464795 # Number of instructions handled by decode system.cpu0.decode.SquashedInsts 475260 # Number of squashed instructions handled by decode system.cpu0.rename.SquashCycles 1410775 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28253862 # Number of cycles rename is idle +system.cpu0.rename.IdleCycles 28253865 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 6710507 # Number of cycles rename is blocking system.cpu0.rename.serializeStallCycles 43964237 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 15899574 # Number of cycles rename is running @@ -658,11 +658,11 @@ system.cpu0.iq.iqSquashedInstsIssued 90659 # Nu system.cpu0.iq.iqSquashedInstsExamined 10605329 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedOperandsExamined 23154537 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 112514 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103827958 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 103827961 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::mean 0.719932 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::stdev 1.414021 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73906108 71.18% 71.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73906111 71.18% 71.18% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::1 10009384 9.64% 80.82% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::2 7640879 7.36% 88.18% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 6355260 6.12% 94.30% # Number of insts issued each cycle @@ -674,7 +674,7 @@ system.cpu0.iq.issued_per_cycle::8 217363 0.21% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103827958 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103827961 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 96059 8.82% 8.82% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 1 0.00% 8.82% # attempts to use FU when none available @@ -747,7 +747,7 @@ system.cpu0.iq.FU_type_0::total 74749052 # Ty system.cpu0.iq.rate 0.702148 # Inst issue rate system.cpu0.iq.fu_busy_cnt 1089511 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.014576 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254491356 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_reads 254491359 # Number of integer instruction queue reads system.cpu0.iq.int_inst_queue_writes 89595521 # Number of integer instruction queue writes system.cpu0.iq.int_inst_queue_wakeup_accesses 72529451 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 14876 # Number of floating instruction queue reads @@ -798,11 +798,11 @@ system.cpu0.iew.wb_fanout 0.574308 # av system.cpu0.commit.commitSquashedInsts 10562082 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 945273 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 353712 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101401285 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 101401288 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::mean 0.674752 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::stdev 1.564672 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74703088 73.67% 73.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74703091 73.67% 73.67% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 12065534 11.90% 85.57% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::2 6043146 5.96% 91.53% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 2565114 2.53% 94.06% # Number of insts commited each cycle @@ -814,7 +814,7 @@ system.cpu0.commit.committed_per_cycle::8 1700075 1.68% 100.00% # N system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101401285 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 101401288 # Number of insts commited each cycle system.cpu0.commit.committedInsts 56174796 # Number of instructions committed system.cpu0.commit.committedOps 68420730 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -861,10 +861,10 @@ system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::total 68420730 # Class of committed instruction system.cpu0.commit.bw_lim_events 1700075 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166296825 # The number of ROB reads +system.cpu0.rob.rob_reads 166296828 # The number of ROB reads system.cpu0.rob.rob_writes 160391499 # The number of ROB writes system.cpu0.timesIdled 400345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2629774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 2629771 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.quiesceCycles 2956130676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu0.committedInsts 56094495 # Number of Instructions Simulated system.cpu0.committedOps 68340429 # Number of Ops (including micro ops) Simulated @@ -872,19 +872,19 @@ system.cpu0.cpi 1.897829 # CP system.cpu0.cpi_total 1.897829 # CPI: Total CPI of All Threads system.cpu0.ipc 0.526918 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.526918 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80764366 # number of integer regfile reads +system.cpu0.int_regfile_reads 80764362 # number of integer regfile reads system.cpu0.int_regfile_writes 46165163 # number of integer regfile writes system.cpu0.fp_regfile_reads 17106 # number of floating regfile reads system.cpu0.fp_regfile_writes 13230 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262463332 # number of cc regfile reads +system.cpu0.cc_regfile_reads 262463335 # number of cc regfile reads system.cpu0.cc_regfile_writes 27226302 # number of cc regfile writes -system.cpu0.misc_regfile_reads 143950426 # number of misc regfile reads +system.cpu0.misc_regfile_reads 143950430 # number of misc regfile reads system.cpu0.misc_regfile_writes 725062 # number of misc regfile writes system.cpu0.dcache.tags.replacements 852281 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42339306 # Total number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 42339308 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 852793 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.647811 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.647814 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.071418 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.913027 # Average occupied blocks per requestor @@ -896,14 +896,14 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189174347 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189174347 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12233621 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 189174355 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189174355 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12233622 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 12935174 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25168795 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7652788 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::total 25168796 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7652789 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 8245651 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15898439 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15898440 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177697 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185293 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 362990 # number of SoftPFReq hits @@ -913,12 +913,12 @@ system.cpu0.dcache.LoadLockedReq_hits::total 446465 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216319 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243020 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 459339 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19886409 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 19886411 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 21180825 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41067234 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20064106 # number of overall hits +system.cpu0.dcache.demand_hits::total 41067236 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20064108 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 21366118 # number of overall hits -system.cpu0.dcache.overall_hits::total 41430224 # number of overall hits +system.cpu0.dcache.overall_hits::total 41430226 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 399335 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 433156 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 832491 # number of ReadReq misses @@ -958,12 +958,12 @@ system.cpu0.dcache.demand_miss_latency::total 178403907084 system.cpu0.dcache.overall_miss_latency::cpu0.data 93671976214 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::cpu1.data 84731930870 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 178403907084 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632956 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 12632957 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 13368330 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26001286 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606512 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26001287 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9606513 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 9991986 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19598498 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19598499 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257155 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 289787 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 546942 # number of SoftPFReq accesses(hits+misses) @@ -973,12 +973,12 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 474225 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216369 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243063 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 459432 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22239468 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 22239470 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 23360316 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45599784 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22496623 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45599786 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22496625 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 23650103 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46146726 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46146728 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031611 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032402 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.032017 # miss rate for ReadReq accesses diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index e69de29bb..be7e45565 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,879 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.061235 # Number of seconds simulated +sim_ticks 61234797500 # Number of ticks simulated +final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 196562 # Simulator instruction rate (inst/s) +host_op_rate 197541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132848546 # Simulator tick rate (ticks/s) +host_mem_usage 399976 # Number of bytes of host memory used +host_seconds 460.94 # Real time elapsed on the host +sim_insts 90602850 # Number of instructions simulated +sim_ops 91054081 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory +system.physmem.bytes_read::total 996672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15573 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 807907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15468329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16276236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 807907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 807907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15468329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16276236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15573 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 15573 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 996672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 996672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 993 # Per bank write bursts +system.physmem.perBankRdBursts::1 890 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts +system.physmem.perBankRdBursts::3 1027 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts +system.physmem.perBankRdBursts::5 1113 # Per bank write bursts +system.physmem.perBankRdBursts::6 1087 # Per bank write bursts +system.physmem.perBankRdBursts::7 1088 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 938 # Per bank write bursts +system.physmem.perBankRdBursts::11 899 # Per bank write bursts +system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::13 867 # Per bank write bursts +system.physmem.perBankRdBursts::14 876 # Per bank write bursts +system.physmem.perBankRdBursts::15 906 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 61234703000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 15573 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 648.213681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 443.714701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.012846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 241 15.70% 15.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.12% 27.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 88 5.73% 33.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.76% 38.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.63% 42.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 84 5.47% 48.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.35% 50.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 51 3.32% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1535 # Bytes accessed per row activation +system.physmem.totQLat 72594750 # Total ticks spent queuing +system.physmem.totMemAccLat 364588500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4661.58 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23411.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.13 # Data bus utilization in percentage +system.physmem.busUtilRead 0.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 14028 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 3932107.04 # Average gap between requests +system.physmem.pageHitRate 90.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63679200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2519893620 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34528365000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41120963895 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.567381 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57430990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2044640000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1755713000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3999315840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2548962765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502857500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41116813260 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.499745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57389143250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2044640000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 20750031 # Number of BP lookups +system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8954908 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8830467 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.610360 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61988 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26205 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 122469595 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 90602850 # Number of instructions committed +system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.351719 # CPI: cycles per instruction +system.cpu.ipc 0.739799 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction +system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91054081 # Class of committed instruction +system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946097 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits +system.cpu.dcache.overall_hits::total 26254912 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses +system.cpu.dcache.overall_misses::total 989219 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks +system.cpu.dcache.writebacks::total 943278 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits +system.cpu.icache.overall_hits::total 27766889 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses +system.cpu.icache.overall_misses::total 801 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27767690 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 5 # number of writebacks +system.cpu.icache.writebacks::total 5 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59427000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59427000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59427000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59427000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59427000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285496 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020572 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312643 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15556 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903167 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903167 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits +system.cpu.l2cache.overall_hits::total 935413 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses +system.cpu.l2cache.overall_misses::total 15581 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066480500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1066480500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57929500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57929500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22043500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22043500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57929500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1088524000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1146453500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57929500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1088524000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1146453500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903429 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903429 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 950994 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 950994 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967541 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967541 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967541 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967541 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15573 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15573 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 921040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 921040500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50052500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50052500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19092500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19092500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940133000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 950994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950828 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 950994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1202498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1029 # Transaction distribution +system.membus.trans_dist::ReadExReq 14544 # Transaction distribution +system.membus.trans_dist::ReadExResp 14544 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1029 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15573 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15573 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15573 # Request fanout histogram +system.membus.reqLayer0.occupancy 21737000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 82128750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index e69de29bb..5fa1b74da 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1214 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.058199 # Number of seconds simulated +sim_ticks 58199030500 # Number of ticks simulated +final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 101249 # Simulator instruction rate (inst/s) +host_op_rate 101754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65047265 # Simulator tick rate (ticks/s) +host_mem_usage 487144 # Number of bytes of host memory used +host_seconds 894.72 # Real time elapsed on the host +sim_insts 90589799 # Number of instructions simulated +sim_ops 91041030 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory +system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory +system.physmem.bytes_written::total 11200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory +system.physmem.num_writes::total 175 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16517 # Number of read requests accepted +system.physmem.writeReqs 175 # Number of write requests accepted +system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1166 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts +system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::3 1031 # Per bank write bursts +system.physmem.perBankRdBursts::4 1061 # Per bank write bursts +system.physmem.perBankRdBursts::5 1122 # Per bank write bursts +system.physmem.perBankRdBursts::6 1094 # Per bank write bursts +system.physmem.perBankRdBursts::7 1089 # Per bank write bursts +system.physmem.perBankRdBursts::8 1025 # Per bank write bursts +system.physmem.perBankRdBursts::9 962 # Per bank write bursts +system.physmem.perBankRdBursts::10 933 # Per bank write bursts +system.physmem.perBankRdBursts::11 900 # Per bank write bursts +system.physmem.perBankRdBursts::12 903 # Per bank write bursts +system.physmem.perBankRdBursts::13 900 # Per bank write bursts +system.physmem.perBankRdBursts::14 1411 # Per bank write bursts +system.physmem.perBankRdBursts::15 910 # Per bank write bursts +system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 6 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts +system.physmem.perBankWrBursts::4 3 # Per bank write bursts +system.physmem.perBankWrBursts::5 16 # Per bank write bursts +system.physmem.perBankWrBursts::6 40 # Per bank write bursts +system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::8 2 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts +system.physmem.perBankWrBursts::11 2 # Per bank write bursts +system.physmem.perBankWrBursts::12 2 # Per bank write bursts +system.physmem.perBankWrBursts::13 17 # Per bank write bursts +system.physmem.perBankWrBursts::14 37 # Per bank write bursts +system.physmem.perBankWrBursts::15 7 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 58199022000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 16517 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 175 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 175730624 # Total ticks spent queuing +system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14651 # Number of row buffer hits during reads +system.physmem.writeRowHits 51 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes +system.physmem.avgGap 3486641.62 # Average gap between requests +system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.381118 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.780705 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 28233538 # Number of BP lookups +system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.numCycles 116398062 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483153288 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41667299 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued +system.cpu.iq.rate 0.870864 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 12822 # number of nop insts executed +system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed +system.cpu.iew.exec_branches 20621209 # Number of branches executed +system.cpu.iew.exec_stores 4915850 # Number of stores executed +system.cpu.iew.exec_rate 0.860065 # Inst execution rate +system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59691637 # num instructions producing a value +system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value +system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle +system.cpu.commit.committedInsts 90602408 # Number of instructions committed +system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 27220755 # Number of memory references committed +system.cpu.commit.loads 22475911 # Number of loads committed +system.cpu.commit.membars 3888 # Number of memory barriers committed +system.cpu.commit.branches 18732305 # Number of branches committed +system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. +system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. +system.cpu.commit.function_calls 56148 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction +system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217947492 # The number of ROB reads +system.cpu.rob.rob_writes 219521309 # The number of ROB writes +system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 90589799 # Number of Instructions Simulated +system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108097873 # number of integer regfile reads +system.cpu.int_regfile_writes 58692304 # number of integer regfile writes +system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.fp_regfile_writes 96 # number of floating regfile writes +system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads +system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes +system.cpu.misc_regfile_reads 28410220 # number of misc regfile reads +system.cpu.misc_regfile_writes 7784 # number of misc regfile writes +system.cpu.dcache.tags.replacements 5470634 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits +system.cpu.dcache.overall_hits::total 18241600 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses +system.cpu.dcache.overall_misses::total 9968505 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks +system.cpu.dcache.writebacks::total 5470634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency +system.cpu.icache.tags.replacements 447 # number of replacements +system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits +system.cpu.icache.overall_hits::total 32273898 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses +system.cpu.icache.overall_misses::total 1145 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 447 # number of writebacks +system.cpu.icache.writebacks::total 447 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 248 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits +system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses +system.cpu.l2cache.overall_misses::total 2260 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks +system.cpu.l2cache.writebacks::total 175 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319939 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 16175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 175 # Transaction distribution +system.membus.trans_dist::CleanEvict 63 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 16759 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 16759 # Request fanout histogram +system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..95463debe 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,520 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.361598 # Number of seconds simulated +sim_ticks 361597758500 # Number of ticks simulated +final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 779266 # Simulator instruction rate (inst/s) +host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1155667536 # Simulator tick rate (ticks/s) +host_mem_usage 379236 # Number of bytes of host memory used +host_seconds 312.89 # Real time elapsed on the host +sim_insts 243825150 # Number of instructions simulated +sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory +system.physmem.bytes_read::total 998592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.numCycles 723195517 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 243825150 # Number of instructions committed +system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses +system.cpu.num_func_calls 4252956 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls +system.cpu.num_int_insts 194726494 # number of integer instructions +system.cpu.num_fp_insts 11630 # number of float instructions +system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read +system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written +system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read +system.cpu.num_fp_register_writes 90 # number of times the floating registers were written +system.cpu.num_mem_refs 105711441 # number of memory refs +system.cpu.num_load_insts 82803521 # Number of load instructions +system.cpu.num_store_insts 22907920 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29302884 # Number of branches fetched +system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction +system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction +system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction +system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses +system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 244420617 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 244420617 # number of overall hits +system.cpu.icache.overall_hits::total 244420617 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses +system.cpu.icache.overall_misses::total 882 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244421499 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244421499 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244421499 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 25 # number of writebacks +system.cpu.icache.writebacks::total 25 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 892700 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 892700 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 924847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 924850 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 924847 # number of overall hits +system.cpu.l2cache.overall_hits::total 924850 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 14567 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 14567 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 879 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 157 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 157 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14724 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 15603 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses +system.cpu.l2cache.overall_misses::total 15603 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 882 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 892857 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 892857 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 939571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 940453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 939571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 940453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311834 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000176 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015671 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.016591 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 14567 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 879 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 157 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14724 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000176 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1036 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram +system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index e69de29bb..7579adace 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,1013 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.065987 # Number of seconds simulated +sim_ticks 65986743500 # Number of ticks simulated +final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 84238 # Simulator instruction rate (inst/s) +host_op_rate 148330 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35183666 # Simulator tick rate (ticks/s) +host_mem_usage 410392 # Number of bytes of host memory used +host_seconds 1875.49 # Real time elapsed on the host +sim_insts 157988547 # Number of instructions simulated +sim_ops 278192464 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory +system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory +system.physmem.bytes_written::total 17920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30622 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory +system.physmem.num_writes::total 280 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30622 # Number of read requests accepted +system.physmem.writeReqs 280 # Number of write requests accepted +system.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue +system.physmem.bytesWritten 16064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1932 # Per bank write bursts +system.physmem.perBankRdBursts::1 2084 # Per bank write bursts +system.physmem.perBankRdBursts::2 2041 # Per bank write bursts +system.physmem.perBankRdBursts::3 1935 # Per bank write bursts +system.physmem.perBankRdBursts::4 2086 # Per bank write bursts +system.physmem.perBankRdBursts::5 1909 # Per bank write bursts +system.physmem.perBankRdBursts::6 1974 # Per bank write bursts +system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::8 1948 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1806 # Per bank write bursts +system.physmem.perBankRdBursts::11 1794 # Per bank write bursts +system.physmem.perBankRdBursts::12 1792 # Per bank write bursts +system.physmem.perBankRdBursts::13 1799 # Per bank write bursts +system.physmem.perBankRdBursts::14 1828 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 107 # Per bank write bursts +system.physmem.perBankWrBursts::2 30 # Per bank write bursts +system.physmem.perBankWrBursts::3 12 # Per bank write bursts +system.physmem.perBankWrBursts::4 60 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 16 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 5 # Per bank write bursts +system.physmem.perBankWrBursts::10 3 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 65986546500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 30622 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.physmem.totQLat 136557750 # Total ticks spent queuing +system.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing +system.physmem.readRowHits 27745 # Number of row buffer hits during reads +system.physmem.writeRowHits 178 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes +system.physmem.avgGap 2135348.73 # Average gap between requests +system.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.125124 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.182663 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 40828848 # Number of BP lookups +system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 131973488 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40712149 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44736331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 501 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 319025181 # Type of FU issued +system.cpu.iq.rate 2.417343 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 135188403 # number of memory reference insts executed +system.cpu.iew.exec_branches 32185799 # Number of branches executed +system.cpu.iew.exec_stores 34371814 # Number of stores executed +system.cpu.iew.exec_rate 2.398114 # Inst execution rate +system.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 314642345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 238446717 # num instructions producing a value +system.cpu.iew.wb_consumers 344411432 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384133 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle +system.cpu.commit.committedInsts 157988547 # Number of instructions committed +system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 122219137 # Number of memory references committed +system.cpu.commit.loads 90779385 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 29309705 # Number of branches committed +system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. +system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. +system.cpu.commit.function_calls 4237596 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction +system.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 445462066 # The number of ROB reads +system.cpu.rob.rob_writes 702797421 # The number of ROB writes +system.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 157988547 # Number of Instructions Simulated +system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.835336 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads +system.cpu.ipc 1.197123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 504041942 # number of integer regfile reads +system.cpu.int_regfile_writes 248656420 # number of integer regfile writes +system.cpu.fp_regfile_reads 4180 # number of floating regfile reads +system.cpu.fp_regfile_writes 782 # number of floating regfile writes +system.cpu.cc_regfile_reads 109261684 # number of cc regfile reads +system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes +system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 2073508 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits +system.cpu.dcache.overall_hits::total 71894591 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses +system.cpu.dcache.overall_misses::total 2787704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks +system.cpu.dcache.writebacks::total 2066969 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.icache.tags.replacements 93 # number of replacements +system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits +system.cpu.icache.overall_hits::total 29996478 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses +system.cpu.icache.overall_misses::total 1445 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 93 # number of writebacks +system.cpu.icache.writebacks::total 93 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1113 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1113 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1113 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1113 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 84684499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 650 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 275.118635 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.598769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.021693 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.628858 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29972 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1995161 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2048067 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2048095 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2048067 # number of overall hits +system.cpu.l2cache.overall_hits::total 2048095 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28982 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1085 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 555 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 555 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29537 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30622 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1085 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29537 # number of overall misses +system.cpu.l2cache.overall_misses::total 30622 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2117059500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 82707500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 43407000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 82707500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2160466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2243174000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 82707500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2160466500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2243174000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066969 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81888 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1113 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995716 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077604 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078717 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077604 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078717 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353922 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974843 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000278 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.974843 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014217 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014731 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.974843 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014217 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014731 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 280 # number of writebacks +system.cpu.l2cache.writebacks::total 280 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 650 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1640 # Transaction distribution +system.membus.trans_dist::WritebackDirty 280 # Transaction distribution +system.membus.trans_dist::CleanEvict 45 # Transaction distribution +system.membus.trans_dist::ReadExReq 28982 # Transaction distribution +system.membus.trans_dist::ReadExResp 28982 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30947 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30947 # Request fanout histogram +system.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index e69de29bb..be41a6e0b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.366199 # Number of seconds simulated +sim_ticks 366199170500 # Number of ticks simulated +final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 433838 # Simulator instruction rate (inst/s) +host_op_rate 763918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1005585249 # Simulator tick rate (ticks/s) +host_mem_usage 405532 # Number of bytes of host memory used +host_seconds 364.17 # Real time elapsed on the host +sim_insts 157988548 # Number of instructions simulated +sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory +system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6528 # Number of bytes written to this memory +system.physmem.bytes_written::total 6528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29241 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.numCycles 732398341 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 157988548 # Number of instructions committed +system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu.num_func_calls 8475189 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls +system.cpu.num_int_insts 278169482 # number of integer instructions +system.cpu.num_fp_insts 40 # number of float instructions +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written +system.cpu.num_fp_register_reads 40 # number of times the floating registers were read +system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written +system.cpu.num_mem_refs 122219137 # number of memory refs +system.cpu.num_load_insts 90779385 # Number of load instructions +system.cpu.num_store_insts 31439752 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 29309705 # Number of branches fetched +system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction +system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction +system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction +system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2062482 # number of writebacks +system.cpu.dcache.writebacks::total 2062482 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses +system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 217695356 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 217695356 # number of overall hits +system.cpu.icache.overall_hits::total 217695356 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses +system.cpu.icache.overall_misses::total 808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 217696164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 217696164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 217696164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 24 # number of writebacks +system.cpu.icache.writebacks::total 24 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 313 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1692 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1960503 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2037588 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2037593 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2037588 # number of overall hits +system.cpu.l2cache.overall_hits::total 2037593 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 803 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 803 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 217 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 217 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29241 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30044 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses +system.cpu.l2cache.overall_misses::total 30044 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 808 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1960720 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1960720 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993812 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000111 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014531 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 102 # number of writebacks +system.cpu.l2cache.writebacks::total 102 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 803 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 217 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29241 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30044 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993812 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 313 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1020 # Transaction distribution +system.membus.trans_dist::WritebackDirty 102 # Transaction distribution +system.membus.trans_dist::CleanEvict 14 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1020 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929344 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30160 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30160 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30160 # Request fanout histogram +system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..d4b67bdd9 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,803 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.412080 # Number of seconds simulated +sim_ticks 412079966500 # Number of ticks simulated +final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 240872 # Simulator instruction rate (inst/s) +host_op_rate 240872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162212982 # Simulator tick rate (ticks/s) +host_mem_usage 251076 # Number of bytes of host memory used +host_seconds 2540.36 # Real time elapsed on the host +sim_insts 611901617 # Number of instructions simulated +sim_ops 611901617 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory +system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377239 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 380043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58588861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58968904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 380043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 380043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45600004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45600004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45600004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 380043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58588861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104568908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379686 # Number of read requests accepted +system.physmem.writeReqs 293607 # Number of write requests accepted +system.physmem.readBursts 379686 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24278080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21824 # Total number of bytes read from write queue +system.physmem.bytesWritten 18789376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24299904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 341 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 23685 # Per bank write bursts +system.physmem.perBankRdBursts::1 23156 # Per bank write bursts +system.physmem.perBankRdBursts::2 23444 # Per bank write bursts +system.physmem.perBankRdBursts::3 24498 # Per bank write bursts +system.physmem.perBankRdBursts::4 25450 # Per bank write bursts +system.physmem.perBankRdBursts::5 23569 # Per bank write bursts +system.physmem.perBankRdBursts::6 23652 # Per bank write bursts +system.physmem.perBankRdBursts::7 23913 # Per bank write bursts +system.physmem.perBankRdBursts::8 23182 # Per bank write bursts +system.physmem.perBankRdBursts::9 23988 # Per bank write bursts +system.physmem.perBankRdBursts::10 24719 # Per bank write bursts +system.physmem.perBankRdBursts::11 22783 # Per bank write bursts +system.physmem.perBankRdBursts::12 23722 # Per bank write bursts +system.physmem.perBankRdBursts::13 24391 # Per bank write bursts +system.physmem.perBankRdBursts::14 22743 # Per bank write bursts +system.physmem.perBankRdBursts::15 22450 # Per bank write bursts +system.physmem.perBankWrBursts::0 17782 # Per bank write bursts +system.physmem.perBankWrBursts::1 17456 # Per bank write bursts +system.physmem.perBankWrBursts::2 17945 # Per bank write bursts +system.physmem.perBankWrBursts::3 18853 # Per bank write bursts +system.physmem.perBankWrBursts::4 19514 # Per bank write bursts +system.physmem.perBankWrBursts::5 18590 # Per bank write bursts +system.physmem.perBankWrBursts::6 18778 # Per bank write bursts +system.physmem.perBankWrBursts::7 18659 # Per bank write bursts +system.physmem.perBankWrBursts::8 18440 # Per bank write bursts +system.physmem.perBankWrBursts::9 18941 # Per bank write bursts +system.physmem.perBankWrBursts::10 19257 # Per bank write bursts +system.physmem.perBankWrBursts::11 18049 # Per bank write bursts +system.physmem.perBankWrBursts::12 18261 # Per bank write bursts +system.physmem.perBankWrBursts::13 18732 # Per bank write bursts +system.physmem.perBankWrBursts::14 17196 # Per bank write bursts +system.physmem.perBankWrBursts::15 17131 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 412079864500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 379686 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 293607 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 142401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.436977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.883041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.731419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50699 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38890 27.31% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13190 9.26% 72.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8518 5.98% 78.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5731 4.02% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3813 2.68% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2946 2.07% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2544 1.79% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16070 11.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142401 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.892595 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.629202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17327 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17327 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.943729 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.871773 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.342990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 17278 99.72% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.19% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 6 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::392-399 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17327 # Writes before turning the bus around for reads +system.physmem.totQLat 4062204500 # Total ticks spent queuing +system.physmem.totMemAccLat 11174923250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10708.47 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29458.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing +system.physmem.readRowHits 314203 # Number of row buffer hits during reads +system.physmem.writeRowHits 216323 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes +system.physmem.avgGap 612036.46 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547933680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298971750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1492662600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 956298960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62025350850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192839650500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285075897780 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.797872 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320257941500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78061587250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 528617880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288432375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1466212800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 946125360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 58968919935 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195520730250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 284634068040 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.725678 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324739070000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 123917421 # Number of BP lookups +system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71578372 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67267052 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.976784 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15041989 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126026 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7056 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4451 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2605 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 734 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 149344684 # DTB read hits +system.cpu.dtb.read_misses 549067 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 149893751 # DTB read accesses +system.cpu.dtb.write_hits 57319581 # DTB write hits +system.cpu.dtb.write_misses 63710 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 57383291 # DTB write accesses +system.cpu.dtb.data_hits 206664265 # DTB hits +system.cpu.dtb.data_misses 612777 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 207277042 # DTB accesses +system.cpu.itb.fetch_hits 226050668 # ITB hits +system.cpu.itb.fetch_misses 48 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 226050716 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.numCycles 824159933 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 611901617 # Number of instructions committed +system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed +system.cpu.discardedOps 12834895 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.346883 # CPI: cycles per instruction +system.cpu.ipc 0.742455 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction +system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction +system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction +system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 611901617 # Class of committed instruction +system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535268 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539364 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.772111 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1636792500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.644038 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666159 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202570428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202570428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202570428 # number of overall hits +system.cpu.dcache.overall_hits::total 202570428 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543875 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543875 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452373 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452373 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452373 # number of overall misses +system.cpu.dcache.overall_misses::total 3452373 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37718879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37718879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47736374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47736374000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85455253500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85455253500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85455253500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85455253500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148812767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148812767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 206022801 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206022801 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206022801 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206022801 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24752.613203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24752.613203 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2339413 # number of writebacks +system.cpu.dcache.writebacks::total 2339413 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143957 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143957 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769052 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769052 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 913009 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 913009 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 913009 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 913009 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764541 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764541 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774823 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774823 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539364 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539364 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539364 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539364 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33202779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33202779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23350926000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23350926000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56553705000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56553705000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56553705000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56553705000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.icache.tags.replacements 3158 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4986 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45336.077417 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.678366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses +system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226045682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226045682 # number of overall hits +system.cpu.icache.overall_hits::total 226045682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4986 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4986 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4986 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4986 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4986 # number of overall misses +system.cpu.icache.overall_misses::total 4986 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 233628500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 233628500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 233628500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 233628500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 233628500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 233628500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226050668 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226050668 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226050668 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226050668 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226050668 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226050668 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46856.899318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46856.899318 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 3158 # number of writebacks +system.cpu.icache.writebacks::total 3158 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4986 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4986 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4986 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4986 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4986 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4986 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 228642500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 228642500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 228642500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 228642500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 228642500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 228642500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45856.899318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45856.899318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 347705 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380135 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.282526 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189119343500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21322.016390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.931124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8022.029650 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.650696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.244813 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32430 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3158 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 571852 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571852 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2539 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2539 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590273 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1590273 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2539 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2162125 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164664 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2539 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2162125 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164664 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206308 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206308 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2447 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2447 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 170931 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 170931 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2447 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 377239 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 379686 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2447 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 377239 # number of overall misses +system.cpu.l2cache.overall_misses::total 379686 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16226611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16226611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194481500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 194481500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13777909500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13777909500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 194481500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30004521000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30199002500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 194481500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30004521000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30199002500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339413 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2339413 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3158 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3158 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 778160 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778160 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4986 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4986 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761204 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1761204 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4986 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539364 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4986 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539364 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265123 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265123 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.490774 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.490774 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097053 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097053 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.490774 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149227 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.490774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149227 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78652.362002 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78652.362002 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79477.523498 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79477.523498 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80605.095038 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80605.095038 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79536.781709 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79477.523498 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79537.166094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79536.781709 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks +system.cpu.l2cache.writebacks::total 293607 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206308 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206308 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2447 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2447 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170931 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170931 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 379686 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2447 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377239 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 379686 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14163531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14163531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170011500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170011500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12068599500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12068599500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170011500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26232131000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26402142500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170011500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26232131000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26402142500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265123 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265123 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490774 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097053 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097053 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5082776 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538426 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761204 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 521216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312762944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 347705 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2892055 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.028759 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2889661 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2394 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2892055 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4883959000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7479000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 173378 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution +system.membus.trans_dist::CleanEvict 51709 # Transaction distribution +system.membus.trans_dist::ReadExReq 206308 # Transaction distribution +system.membus.trans_dist::ReadExResp 206308 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173378 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104688 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104688 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43090752 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 725002 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 725002 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 725002 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021006000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2009290500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index e69de29bb..6ebc4ae73 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,921 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.362632 # Number of seconds simulated +sim_ticks 362631828500 # Number of ticks simulated +final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 177215 # Simulator instruction rate (inst/s) +host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126858592 # Simulator tick rate (ticks/s) +host_mem_usage 271160 # Number of bytes of host memory used +host_seconds 2858.55 # Real time elapsed on the host +sim_insts 506579366 # Number of instructions simulated +sim_ops 548692589 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory +system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory +system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143930 # Number of read requests accepted +system.physmem.writeReqs 97210 # Number of write requests accepted +system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9406 # Per bank write bursts +system.physmem.perBankRdBursts::1 8921 # Per bank write bursts +system.physmem.perBankRdBursts::2 8949 # Per bank write bursts +system.physmem.perBankRdBursts::3 8657 # Per bank write bursts +system.physmem.perBankRdBursts::4 9384 # Per bank write bursts +system.physmem.perBankRdBursts::5 9355 # Per bank write bursts +system.physmem.perBankRdBursts::6 8962 # Per bank write bursts +system.physmem.perBankRdBursts::7 8101 # Per bank write bursts +system.physmem.perBankRdBursts::8 8596 # Per bank write bursts +system.physmem.perBankRdBursts::9 8628 # Per bank write bursts +system.physmem.perBankRdBursts::10 8740 # Per bank write bursts +system.physmem.perBankRdBursts::11 9454 # Per bank write bursts +system.physmem.perBankRdBursts::12 9340 # Per bank write bursts +system.physmem.perBankRdBursts::13 9510 # Per bank write bursts +system.physmem.perBankRdBursts::14 8709 # Per bank write bursts +system.physmem.perBankRdBursts::15 9112 # Per bank write bursts +system.physmem.perBankWrBursts::0 6249 # Per bank write bursts +system.physmem.perBankWrBursts::1 6105 # Per bank write bursts +system.physmem.perBankWrBursts::2 6032 # Per bank write bursts +system.physmem.perBankWrBursts::3 5882 # Per bank write bursts +system.physmem.perBankWrBursts::4 6237 # Per bank write bursts +system.physmem.perBankWrBursts::5 6240 # Per bank write bursts +system.physmem.perBankWrBursts::6 6051 # Per bank write bursts +system.physmem.perBankWrBursts::7 5508 # Per bank write bursts +system.physmem.perBankWrBursts::8 5781 # Per bank write bursts +system.physmem.perBankWrBursts::9 5861 # Per bank write bursts +system.physmem.perBankWrBursts::10 5978 # Per bank write bursts +system.physmem.perBankWrBursts::11 6494 # Per bank write bursts +system.physmem.perBankWrBursts::12 6355 # Per bank write bursts +system.physmem.perBankWrBursts::13 6320 # Per bank write bursts +system.physmem.perBankWrBursts::14 6000 # Per bank write bursts +system.physmem.perBankWrBursts::15 6086 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 362631802500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 143930 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 97210 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads +system.physmem.totQLat 1538291500 # Total ticks spent queuing +system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing +system.physmem.readRowHits 110801 # Number of row buffer hits during reads +system.physmem.writeRowHits 64737 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes +system.physmem.avgGap 1503822.69 # Average gap between requests +system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.841129 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.623774 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 131880511 # Number of BP lookups +system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 725263657 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 506579366 # Number of instructions committed +system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed +system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.431688 # CPI: cycles per instruction +system.cpu.ipc 0.698476 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction +system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction +system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 548692589 # Class of committed instruction +system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1141477 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits +system.cpu.dcache.overall_hits::total 168015632 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses +system.cpu.dcache.overall_misses::total 1557007 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks +system.cpu.dcache.writebacks::total 1069336 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency +system.cpu.icache.tags.replacements 18130 # number of replacements +system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits +system.cpu.icache.overall_hits::total 198770599 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses +system.cpu.icache.overall_misses::total 20001 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 18130 # number of writebacks +system.cpu.icache.writebacks::total 18130 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 112376 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits +system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses +system.cpu.l2cache.overall_misses::total 143945 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks +system.cpu.l2cache.writebacks::total 97210 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112376 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 42981 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution +system.membus.trans_dist::CleanEvict 12558 # Transaction distribution +system.membus.trans_dist::ReadExReq 100949 # Transaction distribution +system.membus.trans_dist::ReadExResp 100949 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 253698 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 253698 # Request fanout histogram +system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e69de29bb..af9a3042a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1238 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.232865 # Number of seconds simulated +sim_ticks 232864525000 # Number of ticks simulated +final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 141001 # Simulator instruction rate (inst/s) +host_op_rate 152754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64987909 # Simulator tick rate (ticks/s) +host_mem_usage 295860 # Number of bytes of host memory used +host_seconds 3583.20 # Real time elapsed on the host +sim_insts 505234934 # Number of instructions simulated +sim_ops 547348155 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory +system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423921 # Number of read requests accepted +system.physmem.writeReqs 292354 # Number of write requests accepted +system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26585 # Per bank write bursts +system.physmem.perBankRdBursts::1 25966 # Per bank write bursts +system.physmem.perBankRdBursts::2 25309 # Per bank write bursts +system.physmem.perBankRdBursts::3 32108 # Per bank write bursts +system.physmem.perBankRdBursts::4 27451 # Per bank write bursts +system.physmem.perBankRdBursts::5 28247 # Per bank write bursts +system.physmem.perBankRdBursts::6 25115 # Per bank write bursts +system.physmem.perBankRdBursts::7 24228 # Per bank write bursts +system.physmem.perBankRdBursts::8 25496 # Per bank write bursts +system.physmem.perBankRdBursts::9 25694 # Per bank write bursts +system.physmem.perBankRdBursts::10 25307 # Per bank write bursts +system.physmem.perBankRdBursts::11 26044 # Per bank write bursts +system.physmem.perBankRdBursts::12 27396 # Per bank write bursts +system.physmem.perBankRdBursts::13 26024 # Per bank write bursts +system.physmem.perBankRdBursts::14 24983 # Per bank write bursts +system.physmem.perBankRdBursts::15 25596 # Per bank write bursts +system.physmem.perBankWrBursts::0 18605 # Per bank write bursts +system.physmem.perBankWrBursts::1 18353 # Per bank write bursts +system.physmem.perBankWrBursts::2 18036 # Per bank write bursts +system.physmem.perBankWrBursts::3 17927 # Per bank write bursts +system.physmem.perBankWrBursts::4 18566 # Per bank write bursts +system.physmem.perBankWrBursts::5 18339 # Per bank write bursts +system.physmem.perBankWrBursts::6 17904 # Per bank write bursts +system.physmem.perBankWrBursts::7 17705 # Per bank write bursts +system.physmem.perBankWrBursts::8 17878 # Per bank write bursts +system.physmem.perBankWrBursts::9 17947 # Per bank write bursts +system.physmem.perBankWrBursts::10 18182 # Per bank write bursts +system.physmem.perBankWrBursts::11 18731 # Per bank write bursts +system.physmem.perBankWrBursts::12 18803 # Per bank write bursts +system.physmem.perBankWrBursts::13 18363 # Per bank write bursts +system.physmem.perBankWrBursts::14 18474 # Per bank write bursts +system.physmem.perBankWrBursts::15 18505 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 232864472500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 423921 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 292354 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads +system.physmem.totQLat 8669198966 # Total ticks spent queuing +system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing +system.physmem.readRowHits 306141 # Number of row buffer hits during reads +system.physmem.writeRowHits 85116 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes +system.physmem.avgGap 325104.84 # Average gap between requests +system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) +system.physmem_0.averagePower 728.002962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states +system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) +system.physmem_1.averagePower 725.972811 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states +system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 174583649 # Number of BP lookups +system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 465729051 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000483863 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306541360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued +system.cpu.iq.rate 1.307470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1492919 # number of nop insts executed +system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263664 # Number of branches executed +system.cpu.iew.exec_stores 60919662 # Number of stores executed +system.cpu.iew.exec_rate 1.284925 # Inst execution rate +system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565798 # num instructions producing a value +system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value +system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle +system.cpu.commit.committedInsts 506578818 # Number of instructions committed +system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 172743503 # Number of memory references committed +system.cpu.commit.loads 115883283 # Number of loads committed +system.cpu.commit.membars 1488542 # Number of memory barriers committed +system.cpu.commit.branches 121552863 # Number of branches committed +system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. +system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. +system.cpu.commit.function_calls 9757362 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction +system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1090292113 # The number of ROB reads +system.cpu.rob.rob_writes 1328334369 # The number of ROB writes +system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 505234934 # Number of Instructions Simulated +system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads +system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610135542 # number of integer regfile reads +system.cpu.int_regfile_writes 327337405 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads +system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes +system.cpu.misc_regfile_reads 217603205 # number of misc regfile reads +system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes +system.cpu.dcache.tags.replacements 2817145 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits +system.cpu.dcache.overall_hits::total 165893629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses +system.cpu.dcache.overall_misses::total 7353956 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks +system.cpu.dcache.writebacks::total 2817145 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency +system.cpu.icache.tags.replacements 76528 # number of replacements +system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits +system.cpu.icache.overall_hits::total 235186472 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses +system.cpu.icache.overall_misses::total 84972 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76528 # number of writebacks +system.cpu.icache.writebacks::total 76528 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 395630 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits +system.cpu.l2cache.overall_hits::total 2722440 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 5096 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5096 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8194 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 8194 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158964 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 158964 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8194 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 164060 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 172254 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8194 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 164060 # number of overall misses +system.cpu.l2cache.overall_misses::total 172254 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 40500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484398500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 484398500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 596844000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 596844000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12095410500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12095410500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 596844000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12579809000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13176653000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 596844000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12579809000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13176653000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350571 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2350571 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 519224 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 519224 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 522011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 522011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77037 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 77037 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295646 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2295646 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 77037 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2817657 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2894694 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 77037 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2817657 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2894694 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009762 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009762 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.106364 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.106364 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069246 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069246 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106364 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.058226 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059507 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106364 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.058226 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059507 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1350 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1350 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76495.483414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks +system.cpu.l2cache.writebacks::total 292354 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4126 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5522 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5531 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5522 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5531 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350840 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 350840 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3700 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8185 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8185 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154838 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154838 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158538 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166723 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158538 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350840 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 517563 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18642506693 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 439500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 439500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 332568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 332568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 547176500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 547176500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10861820000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10861820000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 547176500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11194388000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11741564500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 547176500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11194388000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 950855 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 420223 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution +system.membus.trans_dist::CleanEvict 98859 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33 # Transaction distribution +system.membus.trans_dist::ReadExReq 3697 # Transaction distribution +system.membus.trans_dist::ReadExResp 3697 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 815167 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 815167 # Request fanout histogram +system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..e4f30df65 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.279361 # Number of seconds simulated +sim_ticks 279360903000 # Number of ticks simulated +final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1080925 # Simulator instruction rate (inst/s) +host_op_rate 1170785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 596093333 # Simulator tick rate (ticks/s) +host_mem_usage 259884 # Number of bytes of host memory used +host_seconds 468.65 # Real time elapsed on the host +sim_insts 506578818 # Number of instructions simulated +sim_ops 548692039 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory +system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory +system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 558721807 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 506578818 # Number of instructions committed +system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 121552863 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.trans_dist::ReadReq 630707528 # Transaction distribution +system.membus.trans_dist::ReadResp 632196069 # Transaction distribution +system.membus.trans_dist::WriteReq 54239049 # Transaction distribution +system.membus.trans_dist::WriteResp 54239049 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687926230 # Request fanout histogram +system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 687926230 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index e69de29bb..b0856dd07 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,658 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.708539 # Number of seconds simulated +sim_ticks 708539449500 # Number of ticks simulated +final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 670051 # Simulator instruction rate (inst/s) +host_op_rate 725636 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 940143705 # Simulator tick rate (ticks/s) +host_mem_usage 269876 # Number of bytes of host memory used +host_seconds 753.65 # Real time elapsed on the host +sim_insts 504984064 # Number of instructions simulated +sim_ops 546875315 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory +system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 1417078899 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 504984064 # Number of instructions committed +system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 121552863 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.replacements 1136276 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits +system.cpu.dcache.overall_hits::total 167200190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses +system.cpu.dcache.overall_misses::total 1140372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks +system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency +system.cpu.icache.tags.replacements 9788 # number of replacements +system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits +system.cpu.icache.overall_hits::total 516597066 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses +system.cpu.icache.overall_misses::total 11521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 9788 # number of writebacks +system.cpu.icache.writebacks::total 9788 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 110394 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits +system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses +system.cpu.l2cache.overall_misses::total 142364 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks +system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110394 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 41576 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution +system.membus.trans_dist::CleanEvict 11920 # Transaction distribution +system.membus.trans_dist::ReadExReq 100788 # Transaction distribution +system.membus.trans_dist::ReadExResp 100788 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 250615 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 250615 # Request fanout histogram +system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index e69de29bb..b6e16dfe3 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,1053 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.481958 # Number of seconds simulated +sim_ticks 481957625500 # Number of ticks simulated +final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 86883 # Simulator instruction rate (inst/s) +host_op_rate 160778 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50643012 # Simulator tick rate (ticks/s) +host_mem_usage 314272 # Number of bytes of host memory used +host_seconds 9516.76 # Real time elapsed on the host +sim_insts 826847303 # Number of instructions simulated +sim_ops 1530082520 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory +system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory +system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386855 # Number of read requests accepted +system.physmem.writeReqs 294920 # Number of write requests accepted +system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue +system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24516 # Per bank write bursts +system.physmem.perBankRdBursts::1 26460 # Per bank write bursts +system.physmem.perBankRdBursts::2 24685 # Per bank write bursts +system.physmem.perBankRdBursts::3 24442 # Per bank write bursts +system.physmem.perBankRdBursts::4 23203 # Per bank write bursts +system.physmem.perBankRdBursts::5 23588 # Per bank write bursts +system.physmem.perBankRdBursts::6 24636 # Per bank write bursts +system.physmem.perBankRdBursts::7 24397 # Per bank write bursts +system.physmem.perBankRdBursts::8 23786 # Per bank write bursts +system.physmem.perBankRdBursts::9 23509 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts +system.physmem.perBankRdBursts::11 23975 # Per bank write bursts +system.physmem.perBankRdBursts::12 23290 # Per bank write bursts +system.physmem.perBankRdBursts::13 22963 # Per bank write bursts +system.physmem.perBankRdBursts::14 23965 # Per bank write bursts +system.physmem.perBankRdBursts::15 24296 # Per bank write bursts +system.physmem.perBankWrBursts::0 18881 # Per bank write bursts +system.physmem.perBankWrBursts::1 19925 # Per bank write bursts +system.physmem.perBankWrBursts::2 19022 # Per bank write bursts +system.physmem.perBankWrBursts::3 18969 # Per bank write bursts +system.physmem.perBankWrBursts::4 18086 # Per bank write bursts +system.physmem.perBankWrBursts::5 18421 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19085 # Per bank write bursts +system.physmem.perBankWrBursts::8 18675 # Per bank write bursts +system.physmem.perBankWrBursts::9 17903 # Per bank write bursts +system.physmem.perBankWrBursts::10 18899 # Per bank write bursts +system.physmem.perBankWrBursts::11 17761 # Per bank write bursts +system.physmem.perBankWrBursts::12 17398 # Per bank write bursts +system.physmem.perBankWrBursts::13 16983 # Per bank write bursts +system.physmem.perBankWrBursts::14 17797 # Per bank write bursts +system.physmem.perBankWrBursts::15 17948 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 481957508500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 386855 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 294920 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads +system.physmem.totQLat 4249579000 # Total ticks spent queuing +system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.71 # Data bus utilization in percentage +system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing +system.physmem.readRowHits 315674 # Number of row buffer hits during reads +system.physmem.writeRowHits 215465 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes +system.physmem.avgGap 706915.78 # Average gap between requests +system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.294629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states +system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.434954 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 297786504 # Number of BP lookups +system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 963915252 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 921 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued +system.cpu.iq.rate 2.074089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed +system.cpu.iew.exec_branches 185171662 # Number of branches executed +system.cpu.iew.exec_stores 178831439 # Number of stores executed +system.cpu.iew.exec_rate 2.018648 # Inst execution rate +system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457092334 # num instructions producing a value +system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value +system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle +system.cpu.commit.committedInsts 826847303 # Number of instructions committed +system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 533241508 # Number of memory references committed +system.cpu.commit.loads 384083313 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 149981740 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. +system.cpu.commit.function_calls 17673145 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction +system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3177371770 # The number of ROB reads +system.cpu.rob.rob_writes 4973814894 # The number of ROB writes +system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 826847303 # Number of Instructions Simulated +system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads +system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads +system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes +system.cpu.fp_regfile_reads 239177 # number of floating regfile reads +system.cpu.fp_regfile_writes 8 # number of floating regfile writes +system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads +system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 2545945 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits +system.cpu.dcache.overall_hits::total 421064470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses +system.cpu.dcache.overall_misses::total 3357607 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks +system.cpu.dcache.writebacks::total 2337968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.icache.tags.replacements 4014 # number of replacements +system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits +system.cpu.icache.overall_hits::total 216344175 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses +system.cpu.icache.overall_misses::total 9672 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216353847 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216353847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216353847 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216353847 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 4014 # number of writebacks +system.cpu.icache.writebacks::total 4014 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 355161 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8445.972818 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639730 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005983 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.257751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903464 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32366 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3252 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3252 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588195 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1588195 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3252 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2165592 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2168844 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3252 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2165592 # number of overall hits +system.cpu.l2cache.overall_hits::total 2168844 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1342 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1342 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206686 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206686 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2416 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2416 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 177763 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 177763 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2416 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 384449 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386865 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2416 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 384449 # number of overall misses +system.cpu.l2cache.overall_misses::total 386865 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2044500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 2044500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16338042000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16338042000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195535500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 195535500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14302139500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14302139500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 195535500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30640181500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30835717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 195535500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30640181500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30835717000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337968 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2337968 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3923 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3923 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 784083 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 784083 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5668 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5668 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765958 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1765958 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5668 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2550041 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2555709 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5668 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2550041 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2555709 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808921 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808921 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.263602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.426253 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.426253 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100661 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100661 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.426253 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150762 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151373 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.426253 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150762 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151373 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1523.472429 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1523.472429 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks +system.cpu.l2cache.writebacks::total 294920 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2416 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2416 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 177763 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 177763 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 384449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386865 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2416 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 384449 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386865 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 25553999 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 25553999 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14271182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14271182000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171375500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171375500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12524509500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12524509500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171375500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26795691500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26967067000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171375500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26795691500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 356883 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 180179 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution +system.membus.trans_dist::CleanEvict 57436 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution +system.membus.trans_dist::ReadExReq 206676 # Transaction distribution +system.membus.trans_dist::ReadExResp 206676 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 740563 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 740563 # Request fanout histogram +system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index e69de29bb..74fbe2728 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,127 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.885773 # Number of seconds simulated +sim_ticks 885772926000 # Number of ticks simulated +final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 772132 # Simulator instruction rate (inst/s) +host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 827158459 # Simulator tick rate (ticks/s) +host_mem_usage 268696 # Number of bytes of host memory used +host_seconds 1070.86 # Real time elapsed on the host +sim_insts 826847304 # Number of instructions simulated +sim_ops 1530082521 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory +system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 1771545853 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 826847304 # Number of instructions committed +system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 35346287 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls +system.cpu.num_int_insts 1527470226 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read +system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written +system.cpu.num_mem_refs 533241508 # number of memory refs +system.cpu.num_load_insts 384083313 # Number of load instructions +system.cpu.num_store_insts 149158195 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 149981740 # Number of branches fetched +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction +system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution +system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution +system.membus.trans_dist::WriteReq 149158211 # Transaction distribution +system.membus.trans_dist::WriteResp 149158211 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1601552189 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index e69de29bb..4d088ccd8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.650501 # Number of seconds simulated +sim_ticks 1650501252500 # Number of ticks simulated +final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 482495 # Simulator instruction rate (inst/s) +host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 963127288 # Simulator tick rate (ticks/s) +host_mem_usage 277668 # Number of bytes of host memory used +host_seconds 1713.69 # Real time elapsed on the host +sim_insts 826847304 # Number of instructions simulated +sim_ops 1530082521 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.numCycles 3301002505 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 826847304 # Number of instructions committed +system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 35346287 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls +system.cpu.num_int_insts 1527470226 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read +system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written +system.cpu.num_mem_refs 533241508 # number of memory refs +system.cpu.num_load_insts 384083313 # Number of load instructions +system.cpu.num_store_insts 149158195 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 149981740 # Number of branches fetched +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction +system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction +system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.replacements 2517016 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits +system.cpu.dcache.overall_hits::total 530720441 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses +system.cpu.dcache.overall_misses::total 2521112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks +system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1253 # number of replacements +system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits +system.cpu.icache.overall_hits::total 1068307822 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses +system.cpu.icache.overall_misses::total 2814 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1253 # number of writebacks +system.cpu.icache.writebacks::total 1253 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 348438 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits +system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses +system.cpu.l2cache.overall_misses::total 380855 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks +system.cpu.l2cache.writebacks::total 293208 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 174499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution +system.membus.trans_dist::CleanEvict 53507 # Transaction distribution +system.membus.trans_dist::ReadExReq 206356 # Transaction distribution +system.membus.trans_dist::ReadExResp 206356 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 727569 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..f8a01c82f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,762 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.223533 # Number of seconds simulated +sim_ticks 223532962500 # Number of ticks simulated +final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 234970 # Simulator instruction rate (inst/s) +host_op_rate 234970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131748654 # Simulator tick rate (ticks/s) +host_mem_usage 255168 # Number of bytes of host memory used +host_seconds 1696.66 # Real time elapsed on the host +sim_insts 398664665 # Number of instructions simulated +sim_ops 398664665 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory +system.physmem.bytes_read::total 503680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1114323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1138946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2253269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1114323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1114323 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1114323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1138946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2253269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7870 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 548 # Per bank write bursts +system.physmem.perBankRdBursts::1 675 # Per bank write bursts +system.physmem.perBankRdBursts::2 473 # Per bank write bursts +system.physmem.perBankRdBursts::3 633 # Per bank write bursts +system.physmem.perBankRdBursts::4 474 # Per bank write bursts +system.physmem.perBankRdBursts::5 477 # Per bank write bursts +system.physmem.perBankRdBursts::6 562 # Per bank write bursts +system.physmem.perBankRdBursts::7 560 # Per bank write bursts +system.physmem.perBankRdBursts::8 471 # Per bank write bursts +system.physmem.perBankRdBursts::9 437 # Per bank write bursts +system.physmem.perBankRdBursts::10 354 # Per bank write bursts +system.physmem.perBankRdBursts::11 323 # Per bank write bursts +system.physmem.perBankRdBursts::12 430 # Per bank write bursts +system.physmem.perBankRdBursts::13 556 # Per bank write bursts +system.physmem.perBankRdBursts::14 473 # Per bank write bursts +system.physmem.perBankRdBursts::15 424 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 223532875000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7870 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1541 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 325.149903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.496255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.966466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 538 34.91% 34.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 340 22.06% 56.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 192 12.46% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 106 6.88% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 3.63% 79.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 49 3.18% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.60% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.34% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 11.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1541 # Bytes accessed per row activation +system.physmem.totQLat 51693000 # Total ticks spent queuing +system.physmem.totMemAccLat 199255500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6568.36 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25318.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6320 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 28403160.74 # Average gap between requests +system.physmem.pageHitRate 80.30 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6751080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3683625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34125000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5792542920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 129035577000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 149472420105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.696853 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 214662823500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7464080000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1403552000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26933400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 14599740480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5529545775 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129266276250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 149430056100 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.507329 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 215046035000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7464080000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 45898041 # Number of BP lookups +system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25194489 # Number of BTB lookups +system.cpu.branchPred.BTBHits 18810772 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 74.662249 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8282157 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2248490 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2235007 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13483 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 95357145 # DTB read hits +system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 95357259 # DTB read accesses +system.cpu.dtb.write_hits 73594596 # DTB write hits +system.cpu.dtb.write_misses 852 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 73595448 # DTB write accesses +system.cpu.dtb.data_hits 168951741 # DTB hits +system.cpu.dtb.data_misses 966 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 168952707 # DTB accesses +system.cpu.itb.fetch_hits 96790867 # ITB hits +system.cpu.itb.fetch_misses 1237 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 96792104 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 447065925 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 398664665 # Number of instructions committed +system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2363843 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.121408 # CPI: cycles per instruction +system.cpu.ipc 0.891736 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction +system.cpu.op_class_0::IntAlu 141652567 35.53% 41.33% # Class of committed instruction +system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction +system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.op_class_0::MemRead 94754511 23.77% 81.56% # Class of committed instruction +system.cpu.op_class_0::MemWrite 73520765 18.44% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 398664665 # Class of committed instruction +system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 771 # number of replacements +system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40294.593037 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.617120 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803617 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803617 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167826980 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167826980 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167826980 # number of overall hits +system.cpu.dcache.overall_hits::total 167826980 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5931 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5931 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7114 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7114 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7114 # number of overall misses +system.cpu.dcache.overall_misses::total 7114 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88520000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88520000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 429316500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 429316500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517836500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517836500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517836500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517836500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94313364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94313364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 167834094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167834094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167834094 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167834094 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72791.186393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72791.186393 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 654 # number of writebacks +system.cpu.dcache.writebacks::total 654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2735 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2735 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2949 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2949 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2949 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2949 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 71272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239421000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 239421000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310693000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310693000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310693000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310693000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency +system.cpu.icache.tags.replacements 3190 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18727.882933 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.630000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses +system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 96785699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 96785699 # number of overall hits +system.cpu.icache.overall_hits::total 96785699 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5168 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5168 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5168 # number of overall misses +system.cpu.icache.overall_misses::total 5168 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 316704500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 316704500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 316704500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 316704500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 316704500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 316704500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 96790867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 96790867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 96790867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 96790867 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 96790867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 96790867 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61281.830495 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61281.830495 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 3190 # number of writebacks +system.cpu.icache.writebacks::total 3190 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5168 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5168 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5168 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5168 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5168 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5168 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311536500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311536500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311536500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311536500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311536500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311536500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5270 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.910436 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 372.081904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3407.854115 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.966284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103999 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019591 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.134946 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5270 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3190 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1276 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1276 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1276 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1276 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits +system.cpu.l2cache.overall_hits::total 1463 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3892 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3892 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3892 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7870 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3892 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses +system.cpu.l2cache.overall_misses::total 7870 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 234104000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 234104000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 290385500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 290385500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 68345000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 68345000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 290385500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 302449000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 592834500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 290385500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 302449000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 592834500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3190 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3190 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9333 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9333 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753096 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753096 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.843244 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753096 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.843244 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3892 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3892 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3892 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3892 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 202734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 202734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 251465500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 251465500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59935000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59935000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251465500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 262669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 514134500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251465500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262669000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 514134500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753096 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843244 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753096 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843244 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 13294 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3961 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13526 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22627 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 843328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9333 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9333 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 9333 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10491000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7752000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4733 # Transaction distribution +system.membus.trans_dist::ReadExReq 3137 # Transaction distribution +system.membus.trans_dist::ReadExResp 3137 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7870 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7870 # Request fanout histogram +system.membus.reqLayer0.occupancy 9176500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 41781750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..d9eeb4f16 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1019 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.064189 # Number of seconds simulated +sim_ticks 64188759000 # Number of ticks simulated +final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 189145 # Simulator instruction rate (inst/s) +host_op_rate 189145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32326376 # Simulator tick rate (ticks/s) +host_mem_usage 256256 # Number of bytes of host memory used +host_seconds 1985.65 # Real time elapsed on the host +sim_insts 375574794 # Number of instructions simulated +sim_ops 375574794 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory +system.physmem.bytes_read::total 476160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7440 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3439855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3978267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7418121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3439855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3439855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3439855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3978267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7418121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7440 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7440 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 476160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 476160 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 524 # Per bank write bursts +system.physmem.perBankRdBursts::1 652 # Per bank write bursts +system.physmem.perBankRdBursts::2 450 # Per bank write bursts +system.physmem.perBankRdBursts::3 600 # Per bank write bursts +system.physmem.perBankRdBursts::4 446 # Per bank write bursts +system.physmem.perBankRdBursts::5 454 # Per bank write bursts +system.physmem.perBankRdBursts::6 513 # Per bank write bursts +system.physmem.perBankRdBursts::7 523 # Per bank write bursts +system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::9 408 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts +system.physmem.perBankRdBursts::11 305 # Per bank write bursts +system.physmem.perBankRdBursts::12 414 # Per bank write bursts +system.physmem.perBankRdBursts::13 540 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::15 380 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 64188663500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7440 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.287187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.380841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.777138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 443 32.62% 32.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 304 22.39% 55.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 11.78% 66.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 96 7.07% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 54 3.98% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 38 2.80% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 38 2.80% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.84% 85.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 14.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1358 # Bytes accessed per row activation +system.physmem.totQLat 65294500 # Total ticks spent queuing +system.physmem.totMemAccLat 204794500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8776.14 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27526.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6069 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 8627508.53 # Average gap between requests +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32221800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1996054785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36758466000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42987835170 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.776911 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 61149211250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 890802750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25217400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4192060080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1854861795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36882319500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42961259445 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.362844 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61355238000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2143180000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 47858697 # Number of BP lookups +system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 23334340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19575055 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.889474 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8688210 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1446 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2339152 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2308305 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 30847 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 111425 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 98833092 # DTB read hits +system.cpu.dtb.read_misses 28443 # DTB read misses +system.cpu.dtb.read_acv 867 # DTB read access violations +system.cpu.dtb.read_accesses 98861535 # DTB read accesses +system.cpu.dtb.write_hits 75500788 # DTB write hits +system.cpu.dtb.write_misses 1454 # DTB write misses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_accesses 75502242 # DTB write accesses +system.cpu.dtb.data_hits 174333880 # DTB hits +system.cpu.dtb.data_misses 29897 # DTB misses +system.cpu.dtb.data_acv 870 # DTB access violations +system.cpu.dtb.data_accesses 174363777 # DTB accesses +system.cpu.itb.fetch_hits 46960311 # ITB hits +system.cpu.itb.fetch_misses 430 # ITB misses +system.cpu.itb.fetch_acv 5 # ITB acv +system.cpu.itb.fetch_accesses 46960741 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 128377521 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 47431154 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 424848239 # Number of instructions fetch has processed +system.cpu.fetch.Branches 47858697 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 30571570 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80009353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1247564 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13513 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 46960311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 225671 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 128078159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.317101 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.349648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 53091522 41.45% 41.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4331488 3.38% 44.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6713646 5.24% 50.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5106781 3.99% 54.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 10967794 8.56% 62.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7526071 5.88% 68.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5305239 4.14% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1848793 1.44% 74.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 33186825 25.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 128078159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.372797 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.309366 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42083889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13603478 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 67893810 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3877357 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 619625 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 8883159 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 421926458 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13804 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 619625 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 43653235 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3048927 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 516546 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70101215 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10138611 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 419911173 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439346 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2543427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2848893 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3543199 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 273983157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 552185759 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 393726185 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 158459573 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 14450838 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37562 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15867681 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 99739292 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 76524203 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11895065 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9302116 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 392194254 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 389210938 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 196221 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16619749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7681566 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 128078159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.038855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.181056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17247166 13.47% 13.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19402738 15.15% 28.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008781 17.18% 45.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17964276 14.03% 59.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19060613 14.88% 74.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13269746 10.36% 85.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8793023 6.87% 91.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6106038 4.77% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4225778 3.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 128078159 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 255592 1.41% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 138975 0.77% 2.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 79489 0.44% 2.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 3727 0.02% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3445589 19.00% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1648341 9.09% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8051616 44.40% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4508979 24.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 146987981 37.77% 37.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128295 0.55% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 36418632 9.36% 47.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7354909 1.89% 49.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2800462 0.72% 50.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16556521 4.25% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1584140 0.41% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 99505104 25.57% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 75841313 19.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 389210938 # Type of FU issued +system.cpu.iq.rate 3.031769 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18132308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.046587 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 592570653 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 242193331 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 227932630 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 332257911 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 166691582 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 158290719 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 234731368 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172578297 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19373689 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 4984806 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 93159 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 70985 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3003475 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 382536 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 619625 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1856570 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 132026 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 415917767 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108843 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 99739292 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 76524203 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8227 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 123512 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 70985 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 411741 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230567 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 642308 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 387626106 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98862428 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1584832 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 23723223 # number of nop insts executed +system.cpu.iew.exec_refs 174364706 # number of memory reference insts executed +system.cpu.iew.exec_branches 45864043 # Number of branches executed +system.cpu.iew.exec_stores 75502278 # Number of stores executed +system.cpu.iew.exec_rate 3.019424 # Inst execution rate +system.cpu.iew.wb_sent 386487511 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 386223349 # cumulative count of insts written-back +system.cpu.iew.wb_producers 192322376 # num instructions producing a value +system.cpu.iew.wb_consumers 273878502 # num instructions consuming a value +system.cpu.iew.wb_rate 3.008497 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.702218 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17254297 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569011 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 125612042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.173777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.248518 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 42074654 33.50% 33.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17552788 13.97% 47.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 8725383 6.95% 54.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9055727 7.21% 61.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6223211 4.95% 66.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4119483 3.28% 69.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4738198 3.77% 73.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2406397 1.92% 75.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30716201 24.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 125612042 # Number of insts commited each cycle +system.cpu.commit.committedInsts 398664569 # Number of instructions committed +system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 168275214 # Number of memory references committed +system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 44587530 # Number of branches committed +system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. +system.cpu.commit.function_calls 8007752 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 141652533 35.53% 41.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 94754486 23.77% 81.56% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 73520728 18.44% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction +system.cpu.commit.bw_lim_events 30716201 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 510811730 # The number of ROB reads +system.cpu.rob.rob_writes 834310252 # The number of ROB writes +system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 299362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.341816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.341816 # CPI: Total CPI of All Threads +system.cpu.ipc 2.925550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.925550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 385452871 # number of integer regfile reads +system.cpu.int_regfile_writes 165252221 # number of integer regfile writes +system.cpu.fp_regfile_reads 154536644 # number of floating regfile reads +system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes +system.cpu.misc_regfile_reads 350572 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 776 # number of replacements +system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4176 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36535.653496 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3292.009184 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803713 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501036 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 152572883 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 152572883 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 152572883 # number of overall hits +system.cpu.dcache.overall_hits::total 152572883 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1826 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1826 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19692 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19692 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21518 # number of overall misses +system.cpu.dcache.overall_misses::total 21518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128481000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128481000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1201737956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1201737956 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1330218956 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1330218956 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1330218956 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1330218956 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 79073673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 152594401 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 152594401 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 152594401 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 152594401 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61818.893763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61818.893763 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 50592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 80 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 740 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.367568 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 655 # number of writebacks +system.cpu.dcache.writebacks::total 655 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 838 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 838 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16504 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17342 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74762500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 74762500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249321500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 249321500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 324084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324084000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 324084000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency +system.cpu.icache.tags.replacements 2132 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4060 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11565.188670 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.246133 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894163 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894163 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses +system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 46954666 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 46954666 # number of overall hits +system.cpu.icache.overall_hits::total 46954666 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5645 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5645 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5645 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5645 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5645 # number of overall misses +system.cpu.icache.overall_misses::total 5645 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 370489499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 370489499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 370489499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 370489499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 370489499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 370489499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 46960311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 46960311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 46960311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 46960311 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 46960311 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 46960311 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000120 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000120 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000120 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000120 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000120 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000120 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65631.443578 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65631.443578 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65631.443578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65631.443578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65631.443578 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 2132 # number of writebacks +system.cpu.icache.writebacks::total 2132 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1585 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1585 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1585 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1585 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1585 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1585 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4060 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4060 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4060 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4060 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4060 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4060 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275403500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 275403500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275403500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 275403500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275403500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 275403500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67833.374384 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67833.374384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.635032 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 370.790492 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2968.908882 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 662.008869 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011316 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4847 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2132 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 610 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 610 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 610 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 186 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 796 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 610 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 186 # number of overall hits +system.cpu.l2cache.overall_hits::total 796 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 3128 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3128 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3450 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3450 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 862 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 862 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3990 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7440 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3990 # number of overall misses +system.cpu.l2cache.overall_misses::total 7440 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 243810500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 243810500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262807000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 262807000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71863500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71863500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 262807000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 315674000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 578481000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 262807000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 315674000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 578481000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 655 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 655 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2132 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2132 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3188 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3188 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4060 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4060 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 988 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 988 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4060 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4176 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8236 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4060 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4176 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8236 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981179 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981179 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.849754 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.849754 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.872470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.872470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849754 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955460 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.903351 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849754 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955460 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.903351 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77944.533248 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77944.533248 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76175.942029 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76175.942029 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83368.329466 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83368.329466 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76175.942029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79116.290727 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77752.822581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76175.942029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79116.290727 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77752.822581 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 862 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 862 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3990 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7440 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3990 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7440 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212530500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212530500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 228307000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 228307000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63243500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63243500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 228307000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275774000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 504081000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 228307000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275774000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 504081000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849754 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.872470 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.872470 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849754 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955460 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 11144 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2908 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10252 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 705472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8236 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8236 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8236 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8359000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6090499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4312 # Transaction distribution +system.membus.trans_dist::ReadExReq 3128 # Transaction distribution +system.membus.trans_dist::ReadExResp 3128 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4312 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14880 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 476160 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7440 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7440 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7440 # Request fanout histogram +system.membus.reqLayer0.occupancy 9246500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 39238750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index e69de29bb..fe4a94641 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,534 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.567385 # Number of seconds simulated +sim_ticks 567385356500 # Number of ticks simulated +final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 857568 # Simulator instruction rate (inst/s) +host_op_rate 857568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220503073 # Simulator tick rate (ticks/s) +host_mem_usage 253440 # Number of bytes of host memory used +host_seconds 464.88 # Real time elapsed on the host +sim_insts 398664609 # Number of instructions simulated +sim_ops 398664609 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory +system.physmem.bytes_read::total 459136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 94754490 # DTB read hits +system.cpu.dtb.read_misses 21 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 94754511 # DTB read accesses +system.cpu.dtb.write_hits 73520730 # DTB write hits +system.cpu.dtb.write_misses 35 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 73520765 # DTB write accesses +system.cpu.dtb.data_hits 168275220 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 168275276 # DTB accesses +system.cpu.itb.fetch_hits 398664666 # ITB hits +system.cpu.itb.fetch_misses 173 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 398664839 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 1134770713 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 398664609 # Number of instructions committed +system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses +system.cpu.num_func_calls 16015498 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls +system.cpu.num_int_insts 316365921 # number of integer instructions +system.cpu.num_fp_insts 155295119 # number of float instructions +system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read +system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written +system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read +system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written +system.cpu.num_mem_refs 168275276 # number of memory refs +system.cpu.num_load_insts 94754511 # Number of load instructions +system.cpu.num_store_insts 73520765 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1134770713 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 44587535 # Number of branches fetched +system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction +system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction +system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction +system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction +system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction +system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction +system.cpu.op_class::MemRead 94754511 23.77% 81.56% # Class of executed instruction +system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1769 # number of replacements +system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits +system.cpu.icache.overall_hits::total 398660993 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses +system.cpu.icache.overall_misses::total 3673 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1769 # number of writebacks +system.cpu.icache.writebacks::total 1769 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits +system.cpu.l2cache.overall_hits::total 651 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses +system.cpu.l2cache.overall_misses::total 7174 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4032 # Transaction distribution +system.membus.trans_dist::ReadExReq 3142 # Transaction distribution +system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram +system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index e69de29bb..787a34237 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,882 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.211715 # Number of seconds simulated +sim_ticks 211714953000 # Number of ticks simulated +final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 119593 # Simulator instruction rate (inst/s) +host_op_rate 143584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92732901 # Simulator tick rate (ticks/s) +host_mem_usage 275300 # Number of bytes of host memory used +host_seconds 2283.06 # Real time elapsed on the host +sim_insts 273037857 # Number of instructions simulated +sim_ops 327812214 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1034750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1258447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2293197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1034750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1034750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1034750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1258447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2293197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 630 # Per bank write bursts +system.physmem.perBankRdBursts::1 846 # Per bank write bursts +system.physmem.perBankRdBursts::2 628 # Per bank write bursts +system.physmem.perBankRdBursts::3 541 # Per bank write bursts +system.physmem.perBankRdBursts::4 466 # Per bank write bursts +system.physmem.perBankRdBursts::5 349 # Per bank write bursts +system.physmem.perBankRdBursts::6 171 # Per bank write bursts +system.physmem.perBankRdBursts::7 228 # Per bank write bursts +system.physmem.perBankRdBursts::8 208 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts +system.physmem.perBankRdBursts::10 343 # Per bank write bursts +system.physmem.perBankRdBursts::11 428 # Per bank write bursts +system.physmem.perBankRdBursts::12 553 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts +system.physmem.perBankRdBursts::14 638 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 211714708500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1530 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.067974 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.296863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.878934 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 560 36.60% 36.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 363 23.73% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 160 10.46% 70.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 74 4.84% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.58% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 3.86% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.22% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 28 1.83% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 182 11.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1530 # Bytes accessed per row activation +system.physmem.totQLat 52630500 # Total ticks spent queuing +system.physmem.totMemAccLat 194868000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6937.85 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25687.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6048 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 27908609.08 # Average gap between requests +system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5080320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2772000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5529396150 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 122174691000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 141569591070 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.700877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 203247000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1392729000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13827746400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5726317185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 122001953250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 141595000110 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.820896 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 202960400000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7069400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 32413931 # Number of BP lookups +system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17496692 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12856502 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 73.479615 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6512761 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2303892 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2264485 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 423429906 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037857 # Number of instructions committed +system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2127081 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.550810 # CPI: cycles per instruction +system.cpu.ipc 0.644824 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 104312544 31.82% 31.82% # Class of committed instruction +system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.op_class_0::MemRead 85732248 26.15% 74.87% # Class of committed instruction +system.cpu.op_class_0::MemWrite 82375599 25.13% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 327812214 # Class of committed instruction +system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1355 # number of replacements +system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37379.184619 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.570959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63533 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63533 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168569558 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168569558 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168633091 # number of overall hits +system.cpu.dcache.overall_hits::total 168633091 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2060 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2060 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5226 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 7286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7291 # number of overall misses +system.cpu.dcache.overall_misses::total 7291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 136635000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 136635000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 394688000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 394688000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 531323000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 531323000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 531323000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 531323000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86524167 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86524167 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63538 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63538 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168576844 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168576844 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168640382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168640382 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72923.826517 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72873.817035 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks +system.cpu.dcache.writebacks::total 1010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2356 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2356 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219842000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219842000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 481000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 481000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329758500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329758500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 330239500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 330239500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76600 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency +system.cpu.icache.tags.replacements 38168 # number of replacements +system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40104 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1736.520946 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.744161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939328 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939328 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 69641436 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 69641436 # number of overall hits +system.cpu.icache.overall_hits::total 69641436 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 40105 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 40105 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 40105 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 40105 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 40105 # number of overall misses +system.cpu.icache.overall_misses::total 40105 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 757528000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 757528000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 757528000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 757528000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 757528000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 757528000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69681541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69681541 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69681541 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69681541 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69681541 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69681541 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000576 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000576 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000576 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000576 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000576 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18888.617379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18888.617379 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 38168 # number of writebacks +system.cpu.icache.writebacks::total 38168 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40105 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 40105 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 40105 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 40105 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 40105 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 717424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 717424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 717424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 717424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 717424000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 717424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000576 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000576 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000576 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5648 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.716891 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 353.800339 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.579629 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.321319 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010797 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096667 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128165 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5648 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23251 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36680 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36680 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36680 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 36987 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 36680 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits +system.cpu.l2cache.overall_hits::total 36987 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1351 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1351 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4205 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4205 # number of overall misses +system.cpu.l2cache.overall_misses::total 7630 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215334500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 215334500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257203500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257203500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104684500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 104684500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257203500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 320019000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 577222500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257203500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 320019000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 577222500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23251 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23251 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40105 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 40105 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 40105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 44617 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 40105 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 44617 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085401 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085401 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822777 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822777 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085401 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.931959 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.171011 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085401 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.931959 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.171011 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 42 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 42 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186794500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186794500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222839000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222839000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88850500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88850500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222839000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275645000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222839000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275645000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498484000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085351 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.170025 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085351 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.170025 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 84140 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39625 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118377 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 128756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5009408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 44617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339243 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473458 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29481 66.08% 66.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15136 33.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81248000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 60156998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4732 # Transaction distribution +system.membus.trans_dist::ReadExReq 2854 # Transaction distribution +system.membus.trans_dist::ReadExResp 2854 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7586 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 8883500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 40266000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index e69de29bb..f9a8145d7 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1195 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.111754 # Number of seconds simulated +sim_ticks 111753553500 # Number of ticks simulated +final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 118120 # Simulator instruction rate (inst/s) +host_op_rate 141817 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48346375 # Simulator tick rate (ticks/s) +host_mem_usage 287716 # Number of bytes of host memory used +host_seconds 2311.52 # Real time elapsed on the host +sim_insts 273037220 # Number of instructions simulated +sim_ops 327811602 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory +system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory +system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 84617 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956 # Per bank write bursts +system.physmem.perBankRdBursts::1 811 # Per bank write bursts +system.physmem.perBankRdBursts::2 834 # Per bank write bursts +system.physmem.perBankRdBursts::3 2907 # Per bank write bursts +system.physmem.perBankRdBursts::4 10637 # Per bank write bursts +system.physmem.perBankRdBursts::5 59817 # Per bank write bursts +system.physmem.perBankRdBursts::6 152 # Per bank write bursts +system.physmem.perBankRdBursts::7 259 # Per bank write bursts +system.physmem.perBankRdBursts::8 225 # Per bank write bursts +system.physmem.perBankRdBursts::9 303 # Per bank write bursts +system.physmem.perBankRdBursts::10 3870 # Per bank write bursts +system.physmem.perBankRdBursts::11 811 # Per bank write bursts +system.physmem.perBankRdBursts::12 1141 # Per bank write bursts +system.physmem.perBankRdBursts::13 693 # Per bank write bursts +system.physmem.perBankRdBursts::14 638 # Per bank write bursts +system.physmem.perBankRdBursts::15 563 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 111753395000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 84617 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation +system.physmem.totQLat 818886094 # Total ticks spent queuing +system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.38 # Data bus utilization in percentage +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 63316 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 1320696.73 # Average gap between requests +system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) +system.physmem_0.averagePower 740.214288 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states +system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) +system.physmem_1.averagePower 678.173227 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states +system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 35971731 # Number of BP lookups +system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 223507108 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2465405554 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40533427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued +system.cpu.iq.rate 1.518831 # Inst issue rate +system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 1392 # number of nop insts executed +system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed +system.cpu.iew.exec_branches 31555849 # Number of branches executed +system.cpu.iew.exec_stores 83127503 # Number of stores executed +system.cpu.iew.exec_rate 1.509758 # Inst execution rate +system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151867680 # num instructions producing a value +system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value +system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273037832 # Number of instructions committed +system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 168107892 # Number of memory references committed +system.cpu.commit.loads 85732275 # Number of loads committed +system.cpu.commit.membars 11033 # Number of memory barriers committed +system.cpu.commit.branches 30563526 # Number of branches committed +system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. +system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. +system.cpu.commit.function_calls 6225114 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction +system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 551726691 # The number of ROB reads +system.cpu.rob.rob_writes 686162246 # The number of ROB writes +system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273037220 # Number of Instructions Simulated +system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads +system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325161919 # number of integer regfile reads +system.cpu.int_regfile_writes 134094717 # number of integer regfile writes +system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads +system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads +system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes +system.cpu.misc_regfile_reads 1175447336 # number of misc regfile reads +system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1542955 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits +system.cpu.dcache.overall_hits::total 162054877 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses +system.cpu.dcache.overall_misses::total 3915644 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks +system.cpu.dcache.writebacks::total 1542955 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency +system.cpu.icache.tags.replacements 726201 # number of replacements +system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits +system.cpu.icache.overall_hits::total 81470529 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses +system.cpu.icache.overall_misses::total 732796 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 726201 # number of writebacks +system.cpu.icache.writebacks::total 726201 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 716938 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 716938 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1251135 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1251135 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 716938 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1471099 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2188037 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 716938 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1471099 # number of overall hits +system.cpu.l2cache.overall_hits::total 2188037 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9708 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 9708 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71587 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 71587 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9708 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 72368 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 82076 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9708 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 72368 # number of overall misses +system.cpu.l2cache.overall_misses::total 82076 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 40000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56104500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56104500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 688634000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 688634000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5061315000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5061315000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 688634000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5117419500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 5806053500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 688634000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5117419500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5806053500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 968360 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 968360 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1046226 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1046226 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726646 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 726646 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322722 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1322722 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 726646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1543467 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2270113 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 726646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1543467 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2270113 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.928571 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.928571 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003538 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003538 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013360 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013360 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054121 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054121 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013360 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.046887 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.036155 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013360 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.046887 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.036155 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3076.923077 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3076.923077 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51651 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 51651 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9696 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9696 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71553 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71553 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9696 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 72283 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9696 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 72283 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51651 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133630 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178131300 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 187000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 187000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50303500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50303500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 629910500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 629910500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4630072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4630072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 629910500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4680376000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5310286500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 629910500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4680376000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5488417800 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134350 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 83887 # Transaction distribution +system.membus.trans_dist::UpgradeReq 13 # Transaction distribution +system.membus.trans_dist::ReadExReq 730 # Transaction distribution +system.membus.trans_dist::ReadExResp 730 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 84630 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 84630 # Request fanout histogram +system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..4a706dd92 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.201717 # Number of seconds simulated +sim_ticks 201717314000 # Number of ticks simulated +final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 686314 # Simulator instruction rate (inst/s) +host_op_rate 823996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 507041348 # Simulator tick rate (ticks/s) +host_mem_usage 264028 # Number of bytes of host memory used +host_seconds 397.83 # Real time elapsed on the host +sim_insts 273037595 # Number of instructions simulated +sim_ops 327811950 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory +system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory +system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 403434629 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 273037595 # Number of instructions committed +system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331481 # number of integer instructions +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written +system.cpu.num_mem_refs 168107829 # number of memory refs +system.cpu.num_load_insts 85732235 # Number of load instructions +system.cpu.num_store_insts 82375594 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 30563491 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.trans_dist::ReadReq 434895828 # Transaction distribution +system.membus.trans_dist::ReadResp 434906723 # Transaction distribution +system.membus.trans_dist::WriteReq 82052672 # Transaction distribution +system.membus.trans_dist::WriteResp 82052672 # Transaction distribution +system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution +system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution +system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 517024352 # Request fanout histogram +system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 517024352 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index e69de29bb..3e9613199 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,650 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.517291 # Number of seconds simulated +sim_ticks 517291025500 # Number of ticks simulated +final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 454164 # Simulator instruction rate (inst/s) +host_op_rate 545241 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 861389873 # Simulator tick rate (ticks/s) +host_mem_usage 274016 # Number of bytes of host memory used +host_seconds 600.53 # Real time elapsed on the host +sim_insts 272739286 # Number of instructions simulated +sim_ops 327433744 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory +system.physmem.bytes_read::total 437248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 272739286 # Number of instructions committed +system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses +system.cpu.num_func_calls 12448615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls +system.cpu.num_int_insts 258331537 # number of integer instructions +system.cpu.num_fp_insts 114216705 # number of float instructions +system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written +system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read +system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written +system.cpu.num_mem_refs 168107847 # number of memory refs +system.cpu.num_load_insts 85732248 # Number of load instructions +system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 30563503 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction +system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 327812214 # Class of executed instruction +system.cpu.dcache.tags.replacements 1332 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits +system.cpu.dcache.overall_hits::total 168337827 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses +system.cpu.dcache.overall_misses::total 4479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 998 # number of writebacks +system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency +system.cpu.icache.tags.replacements 13796 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits +system.cpu.icache.overall_hits::total 348644750 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses +system.cpu.icache.overall_misses::total 15603 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 13796 # number of writebacks +system.cpu.icache.writebacks::total 13796 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits +system.cpu.l2cache.overall_hits::total 13249 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses +system.cpu.l2cache.overall_misses::total 6832 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6833 # Request fanout histogram +system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..30b536776 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,800 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.504258 # Number of seconds simulated +sim_ticks 504258263000 # Number of ticks simulated +final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 254365 # Simulator instruction rate (inst/s) +host_op_rate 254365 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 138099861 # Simulator tick rate (ticks/s) +host_mem_usage 257972 # Number of bytes of host memory used +host_seconds 3651.40 # Real time elapsed on the host +sim_insts 928789150 # Number of instructions simulated +sim_ops 928789150 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory +system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292267 # Number of read requests accepted +system.physmem.writeReqs 66683 # Number of write requests accepted +system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18033 # Per bank write bursts +system.physmem.perBankRdBursts::1 18363 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18341 # Per bank write bursts +system.physmem.perBankRdBursts::4 18245 # Per bank write bursts +system.physmem.perBankRdBursts::5 18249 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18290 # Per bank write bursts +system.physmem.perBankRdBursts::8 18231 # Per bank write bursts +system.physmem.perBankRdBursts::9 18232 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18376 # Per bank write bursts +system.physmem.perBankRdBursts::12 18272 # Per bank write bursts +system.physmem.perBankRdBursts::13 18137 # Per bank write bursts +system.physmem.perBankRdBursts::14 18064 # Per bank write bursts +system.physmem.perBankRdBursts::15 18188 # Per bank write bursts +system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankWrBursts::1 4164 # Per bank write bursts +system.physmem.perBankWrBursts::2 4223 # Per bank write bursts +system.physmem.perBankWrBursts::3 4160 # Per bank write bursts +system.physmem.perBankWrBursts::4 4142 # Per bank write bursts +system.physmem.perBankWrBursts::5 4099 # Per bank write bursts +system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::8 4233 # Per bank write bursts +system.physmem.perBankWrBursts::9 4183 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts +system.physmem.perBankWrBursts::11 4241 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4100 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4157 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 504258181000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 292267 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66683 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 3567632750 # Total ticks spent queuing +system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 203404 # Number of row buffer hits during reads +system.physmem.writeRowHits 52048 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes +system.physmem.avgGap 1404814.55 # Average gap between requests +system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ) +system.physmem_0.averagePower 694.703966 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states +system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ) +system.physmem_1.averagePower 694.875219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 123840342 # Number of BP lookups +system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups +system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 237538322 # DTB read hits +system.cpu.dtb.read_misses 198467 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 237736789 # DTB read accesses +system.cpu.dtb.write_hits 98305180 # DTB write hits +system.cpu.dtb.write_misses 7178 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 98312358 # DTB write accesses +system.cpu.dtb.data_hits 335843502 # DTB hits +system.cpu.dtb.data_misses 205645 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 336049147 # DTB accesses +system.cpu.itb.fetch_hits 285763790 # ITB hits +system.cpu.itb.fetch_misses 119 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 285763909 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 1008516526 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 928789150 # Number of instructions committed +system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed +system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.085840 # CPI: cycles per instruction +system.cpu.ipc 0.920946 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction +system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction +system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction +system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 928789150 # Class of committed instruction +system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked +system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 776530 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits +system.cpu.dcache.overall_hits::total 321596153 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses +system.cpu.dcache.overall_misses::total 849082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks +system.cpu.dcache.writebacks::total 88489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.icache.tags.replacements 10567 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits +system.cpu.icache.overall_hits::total 285751480 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses +system.cpu.icache.overall_misses::total 12310 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 10567 # number of writebacks +system.cpu.icache.writebacks::total 10567 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 259940 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 9417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488885 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488885 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9417 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491251 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 500668 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9417 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491251 # number of overall hits +system.cpu.l2cache.overall_hits::total 500668 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2893 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2893 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222730 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222730 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2893 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289375 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 292268 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2893 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289375 # number of overall misses +system.cpu.l2cache.overall_misses::total 292268 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942620000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4942620000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 222699500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 222699500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18537323500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18537323500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222699500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23479943500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23702643000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222699500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23479943500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23702643000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88489 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88489 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10567 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10567 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12310 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 12310 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 711615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 12310 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780626 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792936 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12310 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780626 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792936 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235012 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235012 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312992 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312992 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235012 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370696 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368590 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235012 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370696 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368590 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks +system.cpu.l2cache.writebacks::total 66683 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2893 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2893 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222730 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222730 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2893 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289375 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2893 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289375 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292268 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4276170000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4276170000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193779500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193779500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16310023500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16310023500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259940 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 225622 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191176 # Transaction distribution +system.membus.trans_dist::ReadExReq 66645 # Transaction distribution +system.membus.trans_dist::ReadExResp 66645 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 550126 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 550126 # Request fanout histogram +system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..597ecfa0d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1055 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.174766 # Number of seconds simulated +sim_ticks 174766258500 # Number of ticks simulated +final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 186758 # Simulator instruction rate (inst/s) +host_op_rate 186758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38746139 # Simulator tick rate (ticks/s) +host_mem_usage 259692 # Number of bytes of host memory used +host_seconds 4510.55 # Real time elapsed on the host +sim_insts 842382029 # Number of instructions simulated +sim_ops 842382029 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.writeReqs 66682 # Number of write requests accepted +system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18006 # Per bank write bursts +system.physmem.perBankRdBursts::1 18334 # Per bank write bursts +system.physmem.perBankRdBursts::2 18382 # Per bank write bursts +system.physmem.perBankRdBursts::3 18340 # Per bank write bursts +system.physmem.perBankRdBursts::4 18235 # Per bank write bursts +system.physmem.perBankRdBursts::5 18233 # Per bank write bursts +system.physmem.perBankRdBursts::6 18311 # Per bank write bursts +system.physmem.perBankRdBursts::7 18302 # Per bank write bursts +system.physmem.perBankRdBursts::8 18233 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18220 # Per bank write bursts +system.physmem.perBankRdBursts::11 18388 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18125 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18192 # Per bank write bursts +system.physmem.perBankWrBursts::0 4125 # Per bank write bursts +system.physmem.perBankWrBursts::1 4164 # Per bank write bursts +system.physmem.perBankWrBursts::2 4223 # Per bank write bursts +system.physmem.perBankWrBursts::3 4160 # Per bank write bursts +system.physmem.perBankWrBursts::4 4142 # Per bank write bursts +system.physmem.perBankWrBursts::5 4099 # Per bank write bursts +system.physmem.perBankWrBursts::6 4261 # Per bank write bursts +system.physmem.perBankWrBursts::7 4226 # Per bank write bursts +system.physmem.perBankWrBursts::8 4233 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::10 4148 # Per bank write bursts +system.physmem.perBankWrBursts::11 4241 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4100 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4157 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 174766169000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 292166 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66682 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 3659606000 # Total ticks spent queuing +system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 209802 # Number of row buffer hits during reads +system.physmem.writeRowHits 52054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 487020.04 # Average gap between requests +system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) +system.physmem_0.averagePower 721.044153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) +system.physmem_1.averagePower 720.997890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states +system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 129267026 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 243602185 # DTB read hits +system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 243869852 # DTB read accesses +system.cpu.dtb.write_hits 101634527 # DTB write hits +system.cpu.dtb.write_misses 39608 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 101674135 # DTB write accesses +system.cpu.dtb.data_hits 345236712 # DTB hits +system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 345543987 # DTB accesses +system.cpu.itb.fetch_hits 116217608 # ITB hits +system.cpu.itb.fetch_misses 1594 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 116219202 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 349532518 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued +system.cpu.iq.rate 2.493766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 88070749 # number of nop insts executed +system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159642 # Number of branches executed +system.cpu.iew.exec_stores 101674456 # Number of stores executed +system.cpu.iew.exec_rate 2.491986 # Inst execution rate +system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525000957 # num instructions producing a value +system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value +system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle +system.cpu.commit.committedInsts 928587628 # Number of instructions committed +system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 335811797 # Number of memory references committed +system.cpu.commit.loads 237510597 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 123111018 # Number of branches committed +system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. +system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. +system.cpu.commit.function_calls 18524163 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction +system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1231657697 # The number of ROB reads +system.cpu.rob.rob_writes 1924928764 # The number of ROB writes +system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 842382029 # Number of Instructions Simulated +system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads +system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads +system.cpu.int_regfile_writes 635594518 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 776668 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits +system.cpu.dcache.overall_hits::total 273851866 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses +system.cpu.dcache.overall_misses::total 2447284 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks +system.cpu.dcache.writebacks::total 88604 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.icache.tags.replacements 4617 # number of replacements +system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses +system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 116209358 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 116209358 # number of overall hits +system.cpu.icache.overall_hits::total 116209358 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8250 # number of overall misses +system.cpu.icache.overall_misses::total 8250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354158499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354158499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354158499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354158499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 116217608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 116217608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 116217608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 116217608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 738 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 4617 # number of writebacks +system.cpu.icache.writebacks::total 4617 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1927 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1927 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1927 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6323 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6323 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6323 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6323 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 263974500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 263974500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 259794 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292532 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.126188 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2634.083249 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.428877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911686 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 859 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8617 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4617 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3603 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3603 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489324 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 489324 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3603 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491317 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 494920 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3603 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491317 # number of overall hits +system.cpu.l2cache.overall_hits::total 494920 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66625 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66625 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2720 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2720 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222822 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222822 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2720 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289447 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 292167 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2720 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289447 # number of overall misses +system.cpu.l2cache.overall_misses::total 292167 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5537092500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5537092500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 216561000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 216561000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18014278000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18014278000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 216561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23551370500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23767931500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 216561000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23551370500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23767931500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88604 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88604 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4617 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4617 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 68618 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 68618 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6323 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 6323 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712146 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712146 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6323 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780764 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 787087 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6323 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780764 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 787087 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.970955 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430176 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430176 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312888 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312888 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430176 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370723 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.371200 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430176 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370723 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.371200 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83108.330206 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83108.330206 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79618.014706 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79618.014706 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80846.047518 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80846.047518 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks +system.cpu.l2cache.writebacks::total 66682 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2720 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2720 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222822 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222822 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2720 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292167 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2720 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289447 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292167 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4870842500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4870842500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 189371000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 189371000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15786058000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15786058000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189371000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20656900500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20846271500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189371000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20656900500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20846271500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.371200 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.371200 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution +system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::ReadExReq 66625 # Transaction distribution +system.membus.trans_dist::ReadExResp 66625 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 549958 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 549958 # Request fanout histogram +system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index e69de29bb..b67898874 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.464395 # Number of seconds simulated +sim_ticks 464394627000 # Number of ticks simulated +final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1449486 # Simulator instruction rate (inst/s) +host_op_rate 1449486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 724900195 # Simulator tick rate (ticks/s) +host_mem_usage 247720 # Number of bytes of host memory used +host_seconds 640.63 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory +system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory +system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory +system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789150 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 928789255 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 928789255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 928789255 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution +system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution +system.membus.trans_dist::WriteReq 98301200 # Transaction distribution +system.membus.trans_dist::WriteResp 98301200 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram +system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1264600947 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index e69de29bb..f1f838fe1 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,548 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.288319 # Number of seconds simulated +sim_ticks 1288319411500 # Number of ticks simulated +final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 888638 # Simulator instruction rate (inst/s) +host_op_rate 888638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1232892743 # Simulator tick rate (ticks/s) +host_mem_usage 256432 # Number of bytes of host memory used +host_seconds 1044.96 # Real time elapsed on the host +sim_insts 928587629 # Number of instructions simulated +sim_ops 928587629 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory +system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 237510597 # DTB read hits +system.cpu.dtb.read_misses 194650 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 237705247 # DTB read accesses +system.cpu.dtb.write_hits 98301200 # DTB write hits +system.cpu.dtb.write_misses 6871 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 98308071 # DTB write accesses +system.cpu.dtb.data_hits 335811797 # DTB hits +system.cpu.dtb.data_misses 201521 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 336013318 # DTB accesses +system.cpu.itb.fetch_hits 928789151 # ITB hits +system.cpu.itb.fetch_misses 105 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 928789256 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.numCycles 2576638823 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 928587629 # Number of instructions committed +system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses +system.cpu.num_func_calls 37048314 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls +system.cpu.num_int_insts 822136244 # number of integer instructions +system.cpu.num_fp_insts 33439365 # number of float instructions +system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read +system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read +system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written +system.cpu.num_mem_refs 336013318 # number of memory refs +system.cpu.num_load_insts 237705247 # Number of load instructions +system.cpu.num_store_insts 98308071 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 2576638823 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 123111018 # Number of branches fetched +system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction +system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction +system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction +system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction +system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction +system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction +system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction +system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction +system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks +system.cpu.dcache.writebacks::total 88866 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.icache.tags.replacements 4618 # number of replacements +system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits +system.cpu.icache.overall_hits::total 928782983 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses +system.cpu.icache.overall_misses::total 6168 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 4618 # number of writebacks +system.cpu.icache.writebacks::total 4618 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 258847 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits +system.cpu.l2cache.overall_hits::total 495307 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses +system.cpu.l2cache.overall_misses::total 291389 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks +system.cpu.l2cache.writebacks::total 66683 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 190447 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 548519 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 548519 # Request fanout histogram +system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index e69de29bb..3ea3d5388 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,906 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.489946 # Number of seconds simulated +sim_ticks 489945697500 # Number of ticks simulated +final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 152136 # Simulator instruction rate (inst/s) +host_op_rate 187299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 116346895 # Simulator tick rate (ticks/s) +host_mem_usage 275904 # Number of bytes of host memory used +host_seconds 4211.08 # Real time elapsed on the host +sim_insts 640655085 # Number of instructions simulated +sim_ops 788730744 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory +system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291212 # Number of read requests accepted +system.physmem.writeReqs 66098 # Number of write requests accepted +system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18282 # Per bank write bursts +system.physmem.perBankRdBursts::1 18130 # Per bank write bursts +system.physmem.perBankRdBursts::2 18217 # Per bank write bursts +system.physmem.perBankRdBursts::3 18178 # Per bank write bursts +system.physmem.perBankRdBursts::4 18288 # Per bank write bursts +system.physmem.perBankRdBursts::5 18411 # Per bank write bursts +system.physmem.perBankRdBursts::6 18177 # Per bank write bursts +system.physmem.perBankRdBursts::7 17990 # Per bank write bursts +system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::9 18056 # Per bank write bursts +system.physmem.perBankRdBursts::10 18107 # Per bank write bursts +system.physmem.perBankRdBursts::11 18202 # Per bank write bursts +system.physmem.perBankRdBursts::12 18216 # Per bank write bursts +system.physmem.perBankRdBursts::13 18274 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankWrBursts::0 4171 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4225 # Per bank write bursts +system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 489945603000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 291212 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66098 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads +system.physmem.totQLat 3297540750 # Total ticks spent queuing +system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing +system.physmem.readRowHits 195161 # Number of row buffer hits during reads +system.physmem.writeRowHits 51618 # Number of row buffer hits during writes +system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes +system.physmem.avgGap 1371205.96 # Average gap between requests +system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ) +system.physmem_0.averagePower 695.568361 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states +system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) +system.physmem_1.averagePower 695.442012 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 144591747 # Number of BP lookups +system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups +system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 979891395 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 640655085 # Number of instructions committed +system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed +system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.529515 # CPI: cycles per instruction +system.cpu.ipc 0.653802 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction +system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 788730744 # Class of committed instruction +system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked +system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778302 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits +system.cpu.dcache.overall_hits::total 378436756 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses +system.cpu.dcache.overall_misses::total 851693 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks +system.cpu.dcache.writebacks::total 88712 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency +system.cpu.icache.tags.replacements 24859 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses +system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits +system.cpu.icache.overall_hits::total 252585994 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 26613 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 26613 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 26613 # number of overall misses +system.cpu.icache.overall_misses::total 26613 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 516729500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 516729500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 516729500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 516729500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 516729500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 516729500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 252612607 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 252612607 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 252612607 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 252612607 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 252612607 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 252612607 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19416.431819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 24859 # number of writebacks +system.cpu.icache.writebacks::total 24859 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 490117500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 490117500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 490117500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 490117500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 490117500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 490117500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 258808 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002698 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.910638 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.993675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490486 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490486 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 24049 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493717 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517766 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 24049 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493717 # number of overall hits +system.cpu.l2cache.overall_hits::total 517766 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2564 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2564 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222590 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222590 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2564 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288681 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291245 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2564 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288681 # number of overall misses +system.cpu.l2cache.overall_misses::total 291245 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4932129000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4932129000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 196405000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 196405000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18239788500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18239788500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 196405000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23171917500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23368322500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 196405000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23171917500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23368322500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88712 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88712 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 23528 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 23528 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258808 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 225121 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190682 # Transaction distribution +system.membus.trans_dist::ReadExReq 66091 # Transaction distribution +system.membus.trans_dist::ReadExResp 66091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 547992 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 547992 # Request fanout histogram +system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index e69de29bb..2bcb8651d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1232 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.326731 # Number of seconds simulated +sim_ticks 326731324000 # Number of ticks simulated +final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 120212 # Simulator instruction rate (inst/s) +host_op_rate 147997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61308199 # Simulator tick rate (ticks/s) +host_mem_usage 272964 # Number of bytes of host memory used +host_seconds 5329.33 # Real time elapsed on the host +sim_insts 640649299 # Number of instructions simulated +sim_ops 788724958 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory +system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory +system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 953240 # Number of read requests accepted +system.physmem.writeReqs 66334 # Number of write requests accepted +system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19685 # Per bank write bursts +system.physmem.perBankRdBursts::1 19287 # Per bank write bursts +system.physmem.perBankRdBursts::2 657567 # Per bank write bursts +system.physmem.perBankRdBursts::3 20052 # Per bank write bursts +system.physmem.perBankRdBursts::4 19480 # Per bank write bursts +system.physmem.perBankRdBursts::5 20770 # Per bank write bursts +system.physmem.perBankRdBursts::6 19386 # Per bank write bursts +system.physmem.perBankRdBursts::7 19760 # Per bank write bursts +system.physmem.perBankRdBursts::8 19321 # Per bank write bursts +system.physmem.perBankRdBursts::9 19768 # Per bank write bursts +system.physmem.perBankRdBursts::10 19303 # Per bank write bursts +system.physmem.perBankRdBursts::11 19444 # Per bank write bursts +system.physmem.perBankRdBursts::12 19433 # Per bank write bursts +system.physmem.perBankRdBursts::13 20871 # Per bank write bursts +system.physmem.perBankRdBursts::14 19269 # Per bank write bursts +system.physmem.perBankRdBursts::15 19527 # Per bank write bursts +system.physmem.perBankWrBursts::0 4288 # Per bank write bursts +system.physmem.perBankWrBursts::1 4110 # Per bank write bursts +system.physmem.perBankWrBursts::2 4140 # Per bank write bursts +system.physmem.perBankWrBursts::3 4154 # Per bank write bursts +system.physmem.perBankWrBursts::4 4242 # Per bank write bursts +system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::7 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4095 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4096 # Per bank write bursts +system.physmem.perBankWrBursts::15 4146 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 326731313500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 953240 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66334 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads +system.physmem.totQLat 12733277648 # Total ticks spent queuing +system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.56 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing +system.physmem.readRowHits 805882 # Number of row buffer hits during reads +system.physmem.writeRowHits 26140 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes +system.physmem.avgGap 320458.66 # Average gap between requests +system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) +system.physmem_0.averagePower 771.975754 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states +system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.579541 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states +system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 174663372 # Number of BP lookups +system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 653462649 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued +system.cpu.iq.rate 1.316105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 10252 # number of nop insts executed +system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed +system.cpu.iew.exec_branches 143379422 # Number of branches executed +system.cpu.iew.exec_stores 152688943 # Number of stores executed +system.cpu.iew.exec_rate 1.301023 # Inst execution rate +system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487338276 # num instructions producing a value +system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value +system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle +system.cpu.commit.committedInsts 640654411 # Number of instructions committed +system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 381221434 # Number of memory references committed +system.cpu.commit.loads 252240938 # Number of loads committed +system.cpu.commit.membars 5740 # Number of memory barriers committed +system.cpu.commit.branches 137364860 # Number of branches committed +system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. +system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. +system.cpu.commit.function_calls 19275340 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction +system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1500478116 # The number of ROB reads +system.cpu.rob.rob_writes 1798380886 # The number of ROB writes +system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 640649299 # Number of Instructions Simulated +system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868460109 # number of integer regfile reads +system.cpu.int_regfile_writes 500697086 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads +system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes +system.cpu.misc_regfile_reads 632347849 # number of misc regfile reads +system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.dcache.tags.replacements 2756452 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits +system.cpu.dcache.overall_hits::total 371035352 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses +system.cpu.dcache.overall_misses::total 3447085 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks +system.cpu.dcache.writebacks::total 2756452 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1979880 # number of replacements +system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits +system.cpu.icache.overall_hits::total 245759426 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses +system.cpu.icache.overall_misses::total 1983591 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks +system.cpu.icache.writebacks::total 1979880 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 301370 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits +system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses +system.cpu.l2cache.overall_misses::total 754757 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks +system.cpu.l2cache.writebacks::total 66334 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 951856 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution +system.membus.trans_dist::CleanEvict 227102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::ReadExReq 1383 # Transaction distribution +system.membus.trans_dist::ReadExResp 1383 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1246861 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1246861 # Request fanout histogram +system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..2146f54c4 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.395727 # Number of seconds simulated +sim_ticks 395726778500 # Number of ticks simulated +final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 878754 # Simulator instruction rate (inst/s) +host_op_rate 1081862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 542799023 # Simulator tick rate (ticks/s) +host_mem_usage 264636 # Number of bytes of host memory used +host_seconds 729.05 # Real time elapsed on the host +sim_insts 640654411 # Number of instructions simulated +sim_ops 788730070 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory +system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory +system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory +system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 791453558 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 640654411 # Number of instructions committed +system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 137364860 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.trans_dist::ReadReq 893703778 # Transaction distribution +system.membus.trans_dist::ReadResp 893709517 # Transaction distribution +system.membus.trans_dist::WriteReq 128951477 # Transaction distribution +system.membus.trans_dist::WriteResp 128951477 # Transaction distribution +system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution +system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution +system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram +system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1022670353 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e69de29bb..a634350c6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,659 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.045756 # Number of seconds simulated +sim_ticks 1045756396500 # Number of ticks simulated +final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 554447 # Simulator instruction rate (inst/s) +host_op_rate 681172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 906860836 # Simulator tick rate (ticks/s) +host_mem_usage 273604 # Number of bytes of host memory used +host_seconds 1153.16 # Real time elapsed on the host +sim_insts 639366787 # Number of instructions simulated +sim_ops 785501035 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory +system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2091512793 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 639366787 # Number of instructions committed +system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 137364860 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 788730744 # Class of executed instruction +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks +system.cpu.dcache.writebacks::total 88995 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits +system.cpu.icache.overall_hits::total 643367692 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 8769 # number of writebacks +system.cpu.icache.writebacks::total 8769 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 257772 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits +system.cpu.l2cache.overall_hits::total 501982 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses +system.cpu.l2cache.overall_misses::total 290368 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190094 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 546561 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 546561 # Request fanout histogram +system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..48bad98ae 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,799 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.059447 # Number of seconds simulated +sim_ticks 59447065000 # Number of ticks simulated +final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 249746 # Simulator instruction rate (inst/s) +host_op_rate 249746 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167876675 # Simulator tick rate (ticks/s) +host_mem_usage 256840 # Number of bytes of host memory used +host_seconds 354.11 # Real time elapsed on the host +sim_insts 88438073 # Number of instructions simulated +sim_ops 88438073 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory +system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7326016 # Number of bytes written to this memory +system.physmem.bytes_written::total 7326016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158587 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165350 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114469 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7280965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170732870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178013835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7280965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7280965 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 123235958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 123235958 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 123235958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7280965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170732870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301249793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165350 # Number of read requests accepted +system.physmem.writeReqs 114469 # Number of write requests accepted +system.physmem.readBursts 165350 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114469 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10581952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7323968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10582400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7326016 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10315 # Per bank write bursts +system.physmem.perBankRdBursts::1 10360 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10057 # Per bank write bursts +system.physmem.perBankRdBursts::4 10348 # Per bank write bursts +system.physmem.perBankRdBursts::5 10343 # Per bank write bursts +system.physmem.perBankRdBursts::6 9775 # Per bank write bursts +system.physmem.perBankRdBursts::7 10207 # Per bank write bursts +system.physmem.perBankRdBursts::8 10536 # Per bank write bursts +system.physmem.perBankRdBursts::9 10606 # Per bank write bursts +system.physmem.perBankRdBursts::10 10500 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts +system.physmem.perBankRdBursts::13 10559 # Per bank write bursts +system.physmem.perBankRdBursts::14 10465 # Per bank write bursts +system.physmem.perBankRdBursts::15 10565 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7296 # Per bank write bursts +system.physmem.perBankWrBursts::3 7002 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7186 # Per bank write bursts +system.physmem.perBankWrBursts::6 6833 # Per bank write bursts +system.physmem.perBankWrBursts::7 7099 # Per bank write bursts +system.physmem.perBankWrBursts::8 7226 # Per bank write bursts +system.physmem.perBankWrBursts::9 6999 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 7034 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7299 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::15 7483 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 59447041000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 165350 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 54692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.365172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.328231 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.549756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19615 35.86% 35.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11787 21.55% 57.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5586 10.21% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3666 6.70% 74.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2860 5.23% 79.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2087 3.82% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1603 2.93% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1458 2.67% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6030 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54692 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.476853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.379045 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7039 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.250639 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.234557 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.758479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6275 89.11% 89.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 11 0.16% 89.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.15% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 150 2.13% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.26% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 9 0.13% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads +system.physmem.totQLat 1988923000 # Total ticks spent queuing +system.physmem.totMemAccLat 5089104250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12029.07 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30779.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 123.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 123.24 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing +system.physmem.readRowHits 143858 # Number of row buffer hits during reads +system.physmem.writeRowHits 81218 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.95 # Row buffer hit rate for writes +system.physmem.avgGap 212448.19 # Average gap between requests +system.physmem.pageHitRate 80.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199274040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108730875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636347400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369068400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12411408285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24777095250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42384271290 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.053838 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41070575000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1984840000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16385091250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 213940440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116733375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652860000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372152880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3882347040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13085746785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24185582250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42509362770 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.158080 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40083292000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1984840000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14660042 # Number of BP lookups +system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9866507 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6346497 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 64.323646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708762 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84355 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37443 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31778 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5665 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7605 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20565775 # DTB read hits +system.cpu.dtb.read_misses 97355 # DTB read misses +system.cpu.dtb.read_acv 8 # DTB read access violations +system.cpu.dtb.read_accesses 20663130 # DTB read accesses +system.cpu.dtb.write_hits 14665271 # DTB write hits +system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14674680 # DTB write accesses +system.cpu.dtb.data_hits 35231046 # DTB hits +system.cpu.dtb.data_misses 106764 # DTB misses +system.cpu.dtb.data_acv 8 # DTB access violations +system.cpu.dtb.data_accesses 35337810 # DTB accesses +system.cpu.itb.fetch_hits 25585531 # ITB hits +system.cpu.itb.fetch_misses 5208 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 25590739 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 118894130 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88438073 # Number of instructions committed +system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1097381 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.344377 # CPI: cycles per instruction +system.cpu.ipc 0.743839 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction +system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction +system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction +system.cpu.op_class_0::MemRead 20366786 23.03% 83.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 88438073 # Class of committed instruction +system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200766 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.952954 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 687650500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.673886 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993817 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993817 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333259 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34612040 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34612040 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34612040 # number of overall hits +system.cpu.dcache.overall_hits::total 34612040 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280118 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280118 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369529 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369529 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369529 # number of overall misses +system.cpu.dcache.overall_misses::total 369529 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4770299000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4770299000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21700228000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21700228000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26470527000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26470527000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26470527000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26470527000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20368192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20368192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34981569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34981569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34981569 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34981569 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010564 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010564 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010564 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010564 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71633.151931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71633.151931 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168424 # number of writebacks +system.cpu.dcache.writebacks::total 168424 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136555 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136555 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143563 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143563 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2681247500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2681247500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10975422500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10975422500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13656670000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13656670000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13656670000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13656670000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency +system.cpu.icache.tags.replacements 152872 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154920 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.153176 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42235793500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.382407 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943546 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943546 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1039 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25430610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25430610 # number of overall hits +system.cpu.icache.overall_hits::total 25430610 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 154921 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154921 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 154921 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 154921 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 154921 # number of overall misses +system.cpu.icache.overall_misses::total 154921 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2483739000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2483739000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2483739000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2483739000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2483739000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2483739000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25585531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25585531 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25585531 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25585531 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25585531 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25585531 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006055 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006055 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006055 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006055 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006055 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16032.293879 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16032.293879 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16032.293879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16032.293879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16032.293879 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 152872 # number of writebacks +system.cpu.icache.writebacks::total 152872 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154921 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154921 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154921 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154921 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154921 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154921 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2328819000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2328819000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2328819000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2328819000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2328819000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2328819000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006055 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006055 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006055 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15032.300334 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15032.300334 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 133382 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165492 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.441175 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26350.763451 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2094.967777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1983.317219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.804161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.063933 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.060526 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.928621 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11874 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18854 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 152872 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12681 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12681 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 148157 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 148157 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33594 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 33594 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 148157 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46275 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 194432 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 148157 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46275 # number of overall hits +system.cpu.l2cache.overall_hits::total 194432 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6764 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6764 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27704 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27704 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158587 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165351 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158587 # number of overall misses +system.cpu.l2cache.overall_misses::total 165351 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10626878000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10626878000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 540586000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 540586000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2236085500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2236085500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 540586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12862963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13403549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 540586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12862963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13403549500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168424 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168424 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 152872 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 152872 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143564 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 154921 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 154921 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61298 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 61298 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 154921 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204862 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 359783 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 154921 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204862 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 359783 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911670 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911670 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043661 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043661 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451956 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451956 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043661 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.774116 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.459585 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043661 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.774116 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.459585 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81193.722638 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81193.722638 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79921.052632 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79921.052632 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80713.452931 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80713.452931 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81061.194066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79921.052632 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81109.822999 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81061.194066 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 114469 # number of writebacks +system.cpu.l2cache.writebacks::total 114469 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6764 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6764 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27704 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27704 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158587 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165351 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9318048000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9318048000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 472956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 472956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1959045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1959045500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472956000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11277093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11750049500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472956000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11277093500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11750049500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911670 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911670 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043661 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451956 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451956 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459585 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043661 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774116 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459585 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 713421 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353638 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143564 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61298 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462713 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1073203 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19698688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43588992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133382 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 493165 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090105 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489128 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4037 0.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 493165 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 678006500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 232381497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 34467 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution +system.membus.trans_dist::CleanEvict 14990 # Transaction distribution +system.membus.trans_dist::ReadExReq 130883 # Transaction distribution +system.membus.trans_dist::ReadExResp 130883 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34467 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460159 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17908416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17908416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 294809 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 294809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 294809 # Request fanout histogram +system.membus.reqLayer0.occupancy 822950500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 872961750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..7587af834 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1057 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.022275 # Number of seconds simulated +sim_ticks 22275010500 # Number of ticks simulated +final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 168633 # Simulator instruction rate (inst/s) +host_op_rate 168633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47194651 # Simulator tick rate (ticks/s) +host_mem_usage 258376 # Number of bytes of host memory used +host_seconds 471.98 # Real time elapsed on the host +sim_insts 79591756 # Number of instructions simulated +sim_ops 79591756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory +system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7322816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7322816 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114419 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114419 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18405558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455811951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 474217509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18405558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18405558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 328745793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 328745793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 328745793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18405558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455811951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802963303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165050 # Number of read requests accepted +system.physmem.writeReqs 114419 # Number of write requests accepted +system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114419 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7322816 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10290 # Per bank write bursts +system.physmem.perBankRdBursts::1 10331 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10021 # Per bank write bursts +system.physmem.perBankRdBursts::4 10343 # Per bank write bursts +system.physmem.perBankRdBursts::5 10313 # Per bank write bursts +system.physmem.perBankRdBursts::6 9783 # Per bank write bursts +system.physmem.perBankRdBursts::7 10190 # Per bank write bursts +system.physmem.perBankRdBursts::8 10528 # Per bank write bursts +system.physmem.perBankRdBursts::9 10599 # Per bank write bursts +system.physmem.perBankRdBursts::10 10456 # Per bank write bursts +system.physmem.perBankRdBursts::11 10208 # Per bank write bursts +system.physmem.perBankRdBursts::12 10247 # Per bank write bursts +system.physmem.perBankRdBursts::13 10535 # Per bank write bursts +system.physmem.perBankRdBursts::14 10446 # Per bank write bursts +system.physmem.perBankRdBursts::15 10548 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts +system.physmem.perBankWrBursts::1 7268 # Per bank write bursts +system.physmem.perBankWrBursts::2 7294 # Per bank write bursts +system.physmem.perBankWrBursts::3 7001 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::6 6836 # Per bank write bursts +system.physmem.perBankWrBursts::7 7101 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 7003 # Per bank write bursts +system.physmem.perBankWrBursts::10 7101 # Per bank write bursts +system.physmem.perBankWrBursts::11 7022 # Per bank write bursts +system.physmem.perBankWrBursts::12 6991 # Per bank write bursts +system.physmem.perBankWrBursts::13 7296 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 22274979500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 165050 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114419 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 52304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.896604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.837447 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.790414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18483 35.34% 35.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10568 20.20% 55.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5879 11.24% 66.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2936 5.61% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2943 5.63% 78.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1490 2.85% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2026 3.87% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 952 1.82% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7027 13.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52304 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.609728 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.236069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6988 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.364807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.334911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.053834 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6086 87.07% 87.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.50% 87.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 455 6.51% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 219 3.13% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 100 1.43% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 53 0.76% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 22 0.31% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.16% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads +system.physmem.totQLat 5740232250 # Total ticks spent queuing +system.physmem.totMemAccLat 8834807250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34780.01 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 53530.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 474.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 328.66 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 474.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 328.75 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 6.27 # Data bus utilization in percentage +system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.33 # Average write queue length when enqueuing +system.physmem.readRowHits 145488 # Number of row buffer hits during reads +system.physmem.writeRowHits 81629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.34 # Row buffer hit rate for writes +system.physmem.avgGap 79704.65 # Average gap between requests +system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190428840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103904625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 635177400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368951760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6564184695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7603330500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16920459420 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.821975 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12566232250 # Time in different power states +system.physmem_0.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8959159250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 204618960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111647250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371861280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1454481600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6822625545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7376602500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 16993402335 # Total energy per rank (pJ) +system.physmem_1.averagePower 763.098971 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12188749750 # Time in different power states +system.physmem_1.memoryStateTime::REF 743600000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 16474744 # Number of BP lookups +system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8918177 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7235165 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 81.128296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1973322 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3328 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39379 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31470 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7909 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2657 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 22508484 # DTB read hits +system.cpu.dtb.read_misses 226837 # DTB read misses +system.cpu.dtb.read_acv 16 # DTB read access violations +system.cpu.dtb.read_accesses 22735321 # DTB read accesses +system.cpu.dtb.write_hits 15806842 # DTB write hits +system.cpu.dtb.write_misses 44564 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15851406 # DTB write accesses +system.cpu.dtb.data_hits 38315326 # DTB hits +system.cpu.dtb.data_misses 271401 # DTB misses +system.cpu.dtb.data_acv 20 # DTB access violations +system.cpu.dtb.data_accesses 38586727 # DTB accesses +system.cpu.itb.fetch_hits 13727245 # ITB hits +system.cpu.itb.fetch_misses 29559 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 13756804 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 44550025 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 15536362 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105039044 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16474744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9239957 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27563903 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 886514 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 244 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4722 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 331564 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 78 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13727245 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187963 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 43880130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.393772 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.128235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24375049 55.55% 55.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1515026 3.45% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1375639 3.13% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1503768 3.43% 65.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4189647 9.55% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1825739 4.16% 79.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668569 1.52% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050805 2.39% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7375888 16.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 43880130 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369803 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.357777 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14899233 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9760394 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18283223 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 591754 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 345526 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3700749 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99293 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103056970 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314917 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 345526 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15243567 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4452634 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97322 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18515033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5226048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102057831 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7235 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94720 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 348136 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4717245 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61355857 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123078605 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122759511 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319093 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8808976 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5695 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5747 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2360993 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23135657 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16359365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1252776 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502701 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90727911 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5569 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88607473 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70141 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11141723 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4452155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 986 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43880130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.019307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245631 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17424086 39.71% 39.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5721163 13.04% 52.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5107482 11.64% 64.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4378378 9.98% 74.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4320360 9.85% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2636536 6.01% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1944467 4.43% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1375974 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 971684 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43880130 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243434 9.65% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1167545 46.27% 55.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112329 44.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49382948 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43980 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121151 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120663 0.14% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39093 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22902831 25.85% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15996653 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 88607473 # Type of FU issued +system.cpu.iq.rate 1.988943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523308 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223077288 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101475255 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86832445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420100 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299852 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90825011 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305770 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1671661 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 2859019 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5476 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1745988 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 3024 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 205293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 345526 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1271875 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2754338 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100226384 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125320 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23135657 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16359365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5569 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2752972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 115768 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 151556 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 267324 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87911556 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22736014 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 695917 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 9492904 # number of nop insts executed +system.cpu.iew.exec_refs 38587764 # number of memory reference insts executed +system.cpu.iew.exec_branches 15119893 # Number of branches executed +system.cpu.iew.exec_stores 15851750 # Number of stores executed +system.cpu.iew.exec_rate 1.973322 # Inst execution rate +system.cpu.iew.wb_sent 87534383 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87132297 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33840523 # num instructions producing a value +system.cpu.iew.wb_consumers 44256350 # num instructions consuming a value +system.cpu.iew.wb_rate 1.955830 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764648 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8655398 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 226701 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42610108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.073233 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.886041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21149437 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6275459 14.73% 64.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2900348 6.81% 71.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1740796 4.09% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1682035 3.95% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1127009 2.64% 81.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1202859 2.82% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795530 1.87% 86.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5736635 13.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42610108 # Number of insts commited each cycle +system.cpu.commit.committedInsts 88340672 # Number of instructions committed +system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 34890015 # Number of memory references committed +system.cpu.commit.loads 20276638 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 13754477 # Number of branches committed +system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. +system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. +system.cpu.commit.function_calls 1661057 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction +system.cpu.commit.bw_lim_events 5736635 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132552201 # The number of ROB reads +system.cpu.rob.rob_writes 195265380 # The number of ROB writes +system.cpu.timesIdled 45343 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 669895 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 79591756 # Number of Instructions Simulated +system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.559732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.559732 # CPI: Total CPI of All Threads +system.cpu.ipc 1.786570 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.786570 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116366061 # number of integer regfile reads +system.cpu.int_regfile_writes 57668563 # number of integer regfile writes +system.cpu.fp_regfile_reads 255567 # number of floating regfile reads +system.cpu.fp_regfile_writes 240367 # number of floating regfile writes +system.cpu.misc_regfile_reads 38271 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 201418 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205514 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.365026 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.642288 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2776 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561123 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33984765 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33984765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33984765 # number of overall hits +system.cpu.dcache.overall_hits::total 33984765 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269234 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052254 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052254 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321488 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321488 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321488 # number of overall misses +system.cpu.dcache.overall_misses::total 1321488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17321162000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17321162000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89091667377 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89091667377 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106412829377 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106412829377 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106412829377 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106412829377 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20692876 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35306253 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35306253 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35306253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35306253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013011 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013011 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072006 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072006 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80525.006188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80525.006188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6873080 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 89218 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.036921 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 168806 # number of writebacks +system.cpu.dcache.writebacks::total 168806 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207108 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908866 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908866 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115974 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115974 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115974 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115974 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62126 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62126 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143388 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143388 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205514 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205514 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205514 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205514 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3205966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3205966000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14246299714 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14246299714 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17452265714 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17452265714 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17452265714 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17452265714 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005821 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005821 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005821 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency +system.cpu.icache.tags.replacements 90292 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 92340 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.524063 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18757985500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.963164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936017 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936017 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 384 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13622372 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13622372 # number of overall hits +system.cpu.icache.overall_hits::total 13622372 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 104872 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 104872 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 104872 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 104872 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 104872 # number of overall misses +system.cpu.icache.overall_misses::total 104872 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1921920999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1921920999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1921920999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1921920999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1921920999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1921920999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13727244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13727244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13727244 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13727244 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13727244 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13727244 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007640 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007640 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007640 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007640 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007640 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007640 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18326.350208 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18326.350208 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18326.350208 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18326.350208 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 90292 # number of writebacks +system.cpu.icache.writebacks::total 90292 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12531 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12531 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12531 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12531 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12531 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12531 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92341 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 92341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 92341 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 92341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 92341 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 92341 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1570228500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1570228500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1570228500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1570228500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1570228500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1570228500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006727 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006727 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006727 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006727 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17004.672897 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17004.672897 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 133082 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165175 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.698986 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26800.034004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1869.508141 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1926.294965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.817872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.058786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.933711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32093 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3131 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28315 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 361 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168806 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 90292 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 90292 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12611 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12611 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 85934 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 85934 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34259 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 34259 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85934 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46870 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132804 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85934 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46870 # number of overall hits +system.cpu.l2cache.overall_hits::total 132804 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 130780 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130780 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6407 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 6407 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27864 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 27864 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 6407 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158644 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 165051 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6407 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158644 # number of overall misses +system.cpu.l2cache.overall_misses::total 165051 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13894688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13894688000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 524890500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 524890500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2748099000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2748099000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 524890500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16642787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17167677500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 524890500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16642787000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17167677500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 168806 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 168806 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 90292 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 90292 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143391 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143391 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92341 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 92341 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62123 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 62123 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 92341 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 297855 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 92341 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 297855 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912052 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912052 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069384 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069384 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.448530 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.448530 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069384 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771938 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.554132 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069384 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771938 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.554132 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106244.746903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106244.746903 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81924.535664 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81924.535664 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98625.430663 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98625.430663 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104014.380404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81924.535664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104906.501349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104014.380404 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 114419 # number of writebacks +system.cpu.l2cache.writebacks::total 114419 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27864 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12586888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12586888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 460830500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 460830500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2469459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2469459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460830500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15056347000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15517177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460830500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15056347000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15517177500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912052 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912052 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069384 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448530 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448530 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554132 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771938 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554132 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589565 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291710 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51275 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143391 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62123 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 274973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887419 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11688448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23956480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35644928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133082 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 430937 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009387 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096428 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 426892 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4045 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 430937 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553880500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 138521976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 34270 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution +system.membus.trans_dist::CleanEvict 14728 # Transaction distribution +system.membus.trans_dist::ReadExReq 130780 # Transaction distribution +system.membus.trans_dist::ReadExResp 130780 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34270 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 459247 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17886016 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 294197 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 294197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 294197 # Request fanout histogram +system.membus.reqLayer0.occupancy 776999500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 852713250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index e69de29bb..c91d712f2 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,916 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.056803 # Number of seconds simulated +sim_ticks 56802974500 # Number of ticks simulated +final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 132517 # Simulator instruction rate (inst/s) +host_op_rate 169470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106146312 # Simulator tick rate (ticks/s) +host_mem_usage 275700 # Number of bytes of host memory used +host_seconds 535.14 # Real time elapsed on the host +sim_insts 70915150 # Number of instructions simulated +sim_ops 90690106 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory +system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory +system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128284 # Number of read requests accepted +system.physmem.writeReqs 86215 # Number of write requests accepted +system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8062 # Per bank write bursts +system.physmem.perBankRdBursts::1 8315 # Per bank write bursts +system.physmem.perBankRdBursts::2 8233 # Per bank write bursts +system.physmem.perBankRdBursts::3 8142 # Per bank write bursts +system.physmem.perBankRdBursts::4 8284 # Per bank write bursts +system.physmem.perBankRdBursts::5 8403 # Per bank write bursts +system.physmem.perBankRdBursts::6 8055 # Per bank write bursts +system.physmem.perBankRdBursts::7 7916 # Per bank write bursts +system.physmem.perBankRdBursts::8 8035 # Per bank write bursts +system.physmem.perBankRdBursts::9 7587 # Per bank write bursts +system.physmem.perBankRdBursts::10 7763 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7871 # Per bank write bursts +system.physmem.perBankRdBursts::13 7867 # Per bank write bursts +system.physmem.perBankRdBursts::14 7968 # Per bank write bursts +system.physmem.perBankRdBursts::15 7962 # Per bank write bursts +system.physmem.perBankWrBursts::0 5395 # Per bank write bursts +system.physmem.perBankWrBursts::1 5541 # Per bank write bursts +system.physmem.perBankWrBursts::2 5468 # Per bank write bursts +system.physmem.perBankWrBursts::3 5336 # Per bank write bursts +system.physmem.perBankWrBursts::4 5366 # Per bank write bursts +system.physmem.perBankWrBursts::5 5560 # Per bank write bursts +system.physmem.perBankWrBursts::6 5257 # Per bank write bursts +system.physmem.perBankWrBursts::7 5179 # Per bank write bursts +system.physmem.perBankWrBursts::8 5154 # Per bank write bursts +system.physmem.perBankWrBursts::9 5105 # Per bank write bursts +system.physmem.perBankWrBursts::10 5292 # Per bank write bursts +system.physmem.perBankWrBursts::11 5270 # Per bank write bursts +system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5703 # Per bank write bursts +system.physmem.perBankWrBursts::15 5432 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 56802942500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 128284 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 86215 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads +system.physmem.totQLat 1681541750 # Total ticks spent queuing +system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing +system.physmem.readRowHits 111837 # Number of row buffer hits during reads +system.physmem.writeRowHits 63741 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes +system.physmem.avgGap 264816.82 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.339923 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.487303 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14774616 # Number of BP lookups +system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 113605949 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70915150 # Number of instructions committed +system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.601998 # CPI: cycles per instruction +system.cpu.ipc 0.624220 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction +system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 90690106 # Class of committed instruction +system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156448 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits +system.cpu.dcache.overall_hits::total 42588476 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses +system.cpu.dcache.overall_misses::total 303974 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks +system.cpu.dcache.writebacks::total 128389 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency +system.cpu.icache.tags.replacements 43497 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses +system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits +system.cpu.icache.overall_hits::total 24844377 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses +system.cpu.icache.overall_misses::total 45540 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 43497 # number of writebacks +system.cpu.icache.writebacks::total 43497 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 96391 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits +system.cpu.l2cache.overall_hits::total 77724 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses +system.cpu.l2cache.overall_misses::total 128360 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks +system.cpu.l2cache.writebacks::total 86215 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96391 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 26002 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution +system.membus.trans_dist::CleanEvict 6912 # Transaction distribution +system.membus.trans_dist::ReadExReq 102282 # Transaction distribution +system.membus.trans_dist::ReadExResp 102282 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 221411 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 221411 # Request fanout histogram +system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index e69de29bb..285c58345 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1218 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.033525 # Number of seconds simulated +sim_ticks 33524756000 # Number of ticks simulated +final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 102958 # Simulator instruction rate (inst/s) +host_op_rate 131671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48677985 # Simulator tick rate (ticks/s) +host_mem_usage 277880 # Number of bytes of host memory used +host_seconds 688.70 # Real time elapsed on the host +sim_insts 70907652 # Number of instructions simulated +sim_ops 90682607 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory +system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 153089 # Number of read requests accepted +system.physmem.writeReqs 97140 # Number of write requests accepted +system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9103 # Per bank write bursts +system.physmem.perBankRdBursts::1 9407 # Per bank write bursts +system.physmem.perBankRdBursts::2 9452 # Per bank write bursts +system.physmem.perBankRdBursts::3 11458 # Per bank write bursts +system.physmem.perBankRdBursts::4 10748 # Per bank write bursts +system.physmem.perBankRdBursts::5 11390 # Per bank write bursts +system.physmem.perBankRdBursts::6 10031 # Per bank write bursts +system.physmem.perBankRdBursts::7 8920 # Per bank write bursts +system.physmem.perBankRdBursts::8 9321 # Per bank write bursts +system.physmem.perBankRdBursts::9 9437 # Per bank write bursts +system.physmem.perBankRdBursts::10 9070 # Per bank write bursts +system.physmem.perBankRdBursts::11 9080 # Per bank write bursts +system.physmem.perBankRdBursts::12 8731 # Per bank write bursts +system.physmem.perBankRdBursts::13 8724 # Per bank write bursts +system.physmem.perBankRdBursts::14 9025 # Per bank write bursts +system.physmem.perBankRdBursts::15 9044 # Per bank write bursts +system.physmem.perBankWrBursts::0 5968 # Per bank write bursts +system.physmem.perBankWrBursts::1 6230 # Per bank write bursts +system.physmem.perBankWrBursts::2 6083 # Per bank write bursts +system.physmem.perBankWrBursts::3 6155 # Per bank write bursts +system.physmem.perBankWrBursts::4 6058 # Per bank write bursts +system.physmem.perBankWrBursts::5 6286 # Per bank write bursts +system.physmem.perBankWrBursts::6 6021 # Per bank write bursts +system.physmem.perBankWrBursts::7 5958 # Per bank write bursts +system.physmem.perBankWrBursts::8 5969 # Per bank write bursts +system.physmem.perBankWrBursts::9 6064 # Per bank write bursts +system.physmem.perBankWrBursts::10 6185 # Per bank write bursts +system.physmem.perBankWrBursts::11 5907 # Per bank write bursts +system.physmem.perBankWrBursts::12 6058 # Per bank write bursts +system.physmem.perBankWrBursts::13 6089 # Per bank write bursts +system.physmem.perBankWrBursts::14 6121 # Per bank write bursts +system.physmem.perBankWrBursts::15 5971 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 33524744500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 153089 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 97140 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads +system.physmem.totQLat 6714977565 # Total ticks spent queuing +system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.73 # Data bus utilization in percentage +system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing +system.physmem.readRowHits 120882 # Number of row buffer hits during reads +system.physmem.writeRowHits 32837 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes +system.physmem.avgGap 133976.26 # Average gap between requests +system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) +system.physmem_0.averagePower 766.433942 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states +system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) +system.physmem_1.averagePower 757.956338 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states +system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17055826 # Number of BP lookups +system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 67049513 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453881397 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18149075 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued +system.cpu.iq.rate 1.409676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 15738 # number of nop insts executed +system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed +system.cpu.iew.exec_branches 14212084 # Number of branches executed +system.cpu.iew.exec_stores 20929741 # Number of stores executed +system.cpu.iew.exec_rate 1.397763 # Inst execution rate +system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44994314 # num instructions producing a value +system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value +system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70913204 # Number of instructions committed +system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 43422000 # Number of memory references committed +system.cpu.commit.loads 22866262 # Number of loads committed +system.cpu.commit.membars 15920 # Number of memory barriers committed +system.cpu.commit.branches 13741468 # Number of branches committed +system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. +system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. +system.cpu.commit.function_calls 1679850 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction +system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 157925658 # The number of ROB reads +system.cpu.rob.rob_writes 194257744 # The number of ROB writes +system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70907652 # Number of Instructions Simulated +system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads +system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102008139 # number of integer regfile reads +system.cpu.int_regfile_writes 56630693 # number of integer regfile writes +system.cpu.fp_regfile_reads 48 # number of floating regfile reads +system.cpu.fp_regfile_writes 42 # number of floating regfile writes +system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads +system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes +system.cpu.misc_regfile_reads 44112758 # number of misc regfile reads +system.cpu.misc_regfile_writes 31840 # number of misc regfile writes +system.cpu.dcache.tags.replacements 486293 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits +system.cpu.dcache.overall_hits::total 40299249 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses +system.cpu.dcache.overall_misses::total 1653828 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks +system.cpu.dcache.writebacks::total 486293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency +system.cpu.icache.tags.replacements 325000 # number of replacements +system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits +system.cpu.icache.overall_hits::total 22083387 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334707 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334707 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334707 # number of overall misses +system.cpu.icache.overall_misses::total 334707 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3526570179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3526570179 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3526570179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3526570179 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3526570179 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3526570179 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22418094 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22418094 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22418094 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22418094 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22418094 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22418094 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325000 # number of writebacks +system.cpu.icache.writebacks::total 325000 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 325529 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 325529 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 325529 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 325529 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 128177 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300687 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 300687 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 314576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437780 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 752356 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 314576 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437780 # number of overall hits +system.cpu.l2cache.overall_hits::total 752356 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 11519 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11519 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10935 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10935 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 37506 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 37506 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10935 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 49025 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 59960 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10935 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 49025 # number of overall misses +system.cpu.l2cache.overall_misses::total 59960 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1190791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1190791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 838826500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 838826500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3069049000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3069049000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 838826500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4259840000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 5098666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 838826500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4259840000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5098666500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 260314 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 260314 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 470737 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 470737 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148612 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148612 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325511 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 325511 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 338193 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 338193 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 325511 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 486805 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 812316 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 325511 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 486805 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 812316 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077511 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.077511 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.033593 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.033593 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.110901 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.110901 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.100708 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.073814 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.100708 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.073814 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103376.247938 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103376.247938 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76710.242341 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76710.242341 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81828.214152 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81828.214152 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks +system.cpu.l2cache.writebacks::total 97140 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3282 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3310 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3282 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3310 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112662 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112662 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8337 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8337 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10907 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10907 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 37406 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 37406 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10907 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 45743 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 56650 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10907 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 45743 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112662 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169312 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10325101509 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 232500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 232500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 662233000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 662233000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 771578500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 771578500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2838075000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2838075000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 771578500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3500308000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4271886500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 771578500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3500308000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14596988009 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318692 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 144751 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution +system.membus.trans_dist::CleanEvict 28117 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 8337 # Transaction distribution +system.membus.trans_dist::ReadExResp 8337 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 278362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 278362 # Request fanout histogram +system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..a81e64eec 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,807 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.208778 # Number of seconds simulated +sim_ticks 1208777694500 # Number of ticks simulated +final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 239767 # Simulator instruction rate (inst/s) +host_op_rate 239767 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158688267 # Simulator tick rate (ticks/s) +host_mem_usage 248760 # Number of bytes of host memory used +host_seconds 7617.31 # Real time elapsed on the host +sim_insts 1826378509 # Number of instructions simulated +sim_ops 1826378509 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory +system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65416896 # Number of bytes written to this memory +system.physmem.bytes_written::total 65416896 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952658 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1953616 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022139 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022139 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103385521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103436244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54118219 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54118219 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54118219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103385521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157554463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1953616 # Number of read requests accepted +system.physmem.writeReqs 1022139 # Number of write requests accepted +system.physmem.readBursts 1953616 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1022139 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124948416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83008 # Total number of bytes read from write queue +system.physmem.bytesWritten 65415616 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125031424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65416896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1297 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118316 # Per bank write bursts +system.physmem.perBankRdBursts::1 113525 # Per bank write bursts +system.physmem.perBankRdBursts::2 115740 # Per bank write bursts +system.physmem.perBankRdBursts::3 117258 # Per bank write bursts +system.physmem.perBankRdBursts::4 117310 # Per bank write bursts +system.physmem.perBankRdBursts::5 117126 # Per bank write bursts +system.physmem.perBankRdBursts::6 119402 # Per bank write bursts +system.physmem.perBankRdBursts::7 124113 # Per bank write bursts +system.physmem.perBankRdBursts::8 126650 # Per bank write bursts +system.physmem.perBankRdBursts::9 129582 # Per bank write bursts +system.physmem.perBankRdBursts::10 128169 # Per bank write bursts +system.physmem.perBankRdBursts::11 129917 # Per bank write bursts +system.physmem.perBankRdBursts::12 125580 # Per bank write bursts +system.physmem.perBankRdBursts::13 124837 # Per bank write bursts +system.physmem.perBankRdBursts::14 122150 # Per bank write bursts +system.physmem.perBankRdBursts::15 122644 # Per bank write bursts +system.physmem.perBankWrBursts::0 61421 # Per bank write bursts +system.physmem.perBankWrBursts::1 61661 # Per bank write bursts +system.physmem.perBankWrBursts::2 60724 # Per bank write bursts +system.physmem.perBankWrBursts::3 61398 # Per bank write bursts +system.physmem.perBankWrBursts::4 61819 # Per bank write bursts +system.physmem.perBankWrBursts::5 63309 # Per bank write bursts +system.physmem.perBankWrBursts::6 64356 # Per bank write bursts +system.physmem.perBankWrBursts::7 65855 # Per bank write bursts +system.physmem.perBankWrBursts::8 65577 # Per bank write bursts +system.physmem.perBankWrBursts::9 66031 # Per bank write bursts +system.physmem.perBankWrBursts::10 65643 # Per bank write bursts +system.physmem.perBankWrBursts::11 65945 # Per bank write bursts +system.physmem.perBankWrBursts::12 64508 # Per bank write bursts +system.physmem.perBankWrBursts::13 64526 # Per bank write bursts +system.physmem.perBankWrBursts::14 64900 # Per bank write bursts +system.physmem.perBankWrBursts::15 64446 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1208777578000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1953616 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1022139 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1830097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1831457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.940817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.136003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.529919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452947 79.33% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261995 14.31% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48664 2.66% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20593 1.12% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13175 0.72% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7238 0.40% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5438 0.30% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4580 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16827 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.747643 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 146.947369 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59453 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 9 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 9 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.145620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.109391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.119268 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27453 46.05% 46.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1268 2.13% 48.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26337 44.18% 92.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4007 6.72% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 455 0.76% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 71 0.12% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59614 # Writes before turning the bus around for reads +system.physmem.totQLat 36537628750 # Total ticks spent queuing +system.physmem.totMemAccLat 73143610000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18714.99 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37464.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 723773 # Number of row buffer hits during reads +system.physmem.writeRowHits 419204 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes +system.physmem.avgGap 406208.70 # Average gap between requests +system.physmem.pageHitRate 38.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6714376200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3663598125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353738600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243518640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415074736440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361165338750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876166703955 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.837554 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 598070170000 # Time in different power states +system.physmem_0.memoryStateTime::REF 40363700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 570342873000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7131423600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3891153750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7874224800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379812480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78951397200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426560774805 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351089866500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 878878653135 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.081103 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581228871000 # Time in different power states +system.physmem_1.memoryStateTime::REF 40363700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 246097965 # Number of BP lookups +system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167640085 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165196337 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.542265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18413332 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104391 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 297 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 67 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 98 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 452860657 # DTB read hits +system.cpu.dtb.read_misses 4979867 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 457840524 # DTB read accesses +system.cpu.dtb.write_hits 161378231 # DTB write hits +system.cpu.dtb.write_misses 1709431 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 163087662 # DTB write accesses +system.cpu.dtb.data_hits 614238888 # DTB hits +system.cpu.dtb.data_misses 6689298 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 620928186 # DTB accesses +system.cpu.itb.fetch_hits 597989612 # ITB hits +system.cpu.itb.fetch_misses 19 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 597989631 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 2417555389 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1826378509 # Number of instructions committed +system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed +system.cpu.discardedOps 51811935 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.323688 # CPI: cycles per instruction +system.cpu.ipc 0.755465 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction +system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction +system.cpu.op_class_0::MemRead 449492741 24.61% 91.11% # Class of committed instruction +system.cpu.op_class_0::MemWrite 162429806 8.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1826378509 # Class of committed instruction +system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121974 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126070 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.914337 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726355 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158481991 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601538856 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601538856 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601538856 # number of overall hits +system.cpu.dcache.overall_hits::total 601538856 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289538 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289538 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246511 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246511 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536049 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536049 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536049 # number of overall misses +system.cpu.dcache.overall_misses::total 9536049 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185480529000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108417025500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293897554500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293897554500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293897554500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293897554500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450346403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450346403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 611074905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611074905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611074905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611074905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30819.635522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30819.635522 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3686603 # number of writebacks +system.cpu.dcache.writebacks::total 3686603 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50808 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50808 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359171 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359171 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409979 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409979 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409979 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409979 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238730 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887340 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887340 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126070 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126070 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126070 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126070 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83258719000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83258719000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260269787000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260269787000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624205.275574 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 750.173547 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 597988654 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 597988654 # number of overall hits +system.cpu.icache.overall_hits::total 597988654 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.icache.overall_misses::total 958 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 76338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 76338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 76338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 76338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 76338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 76338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 597989612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 597989612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 597989612 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 597989612 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 597989612 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 597989612 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 79684.759916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 79684.759916 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 3 # number of writebacks +system.cpu.icache.writebacks::total 3 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75380000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75380000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75380000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75380000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75380000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75380000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 1920891 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1950696 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.386949 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 89219766000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.817395 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.451611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001307 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.485965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29805 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1217 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12865 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106830 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106830 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066582 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6066582 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7173412 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7173412 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7173412 # number of overall hits +system.cpu.l2cache.overall_hits::total 7173412 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 780510 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 780510 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 958 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 958 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1172148 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1172148 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 958 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1952658 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1953616 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 958 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1952658 # number of overall misses +system.cpu.l2cache.overall_misses::total 1953616 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68734828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 68734828000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73941000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 73941000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 73941000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 171234996000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 73941000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 171234996000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3686603 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3686603 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887340 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887340 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 958 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238730 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7238730 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126070 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127028 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9126070 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127028 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413550 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413550 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161927 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161927 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.213965 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214047 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213965 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214047 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1022139 # number of writebacks +system.cpu.l2cache.writebacks::total 1022139 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780510 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780510 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 958 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172148 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172148 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1953616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1953616 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60929728000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60929728000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64361000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64361000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90704747000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90704747000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64361000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64361000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413550 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413550 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18249005 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121977 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6334123 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238730 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820072576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920891 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11047919 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11046651 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11047919 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811108500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1173106 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution +system.membus.trans_dist::CleanEvict 897726 # Transaction distribution +system.membus.trans_dist::ReadExReq 780510 # Transaction distribution +system.membus.trans_dist::ReadExResp 780510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173106 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827097 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827097 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190448320 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3873481 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873481 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3873481 # Request fanout histogram +system.membus.reqLayer0.occupancy 8428417500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 10685410500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..12610c445 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1095 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.669588 # Number of seconds simulated +sim_ticks 669587683000 # Number of ticks simulated +final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 147374 # Simulator instruction rate (inst/s) +host_op_rate 147374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56841738 # Simulator tick rate (ticks/s) +host_mem_usage 250296 # Number of bytes of host memory used +host_seconds 11779.86 # Real time elapsed on the host +sim_insts 1736043781 # Number of instructions simulated +sim_ops 1736043781 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory +system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65555456 # Number of bytes written to this memory +system.physmem.bytes_written::total 65555456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960774 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961723 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187413149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187503855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97904214 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97904214 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97904214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187413149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 285408070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961723 # Number of read requests accepted +system.physmem.writeReqs 1024304 # Number of write requests accepted +system.physmem.readBursts 1961723 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125465280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84992 # Total number of bytes read from write queue +system.physmem.bytesWritten 65553920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125550272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65555456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1328 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118674 # Per bank write bursts +system.physmem.perBankRdBursts::1 113905 # Per bank write bursts +system.physmem.perBankRdBursts::2 116110 # Per bank write bursts +system.physmem.perBankRdBursts::3 117640 # Per bank write bursts +system.physmem.perBankRdBursts::4 117758 # Per bank write bursts +system.physmem.perBankRdBursts::5 117504 # Per bank write bursts +system.physmem.perBankRdBursts::6 119855 # Per bank write bursts +system.physmem.perBankRdBursts::7 124644 # Per bank write bursts +system.physmem.perBankRdBursts::8 127350 # Per bank write bursts +system.physmem.perBankRdBursts::9 130115 # Per bank write bursts +system.physmem.perBankRdBursts::10 128783 # Per bank write bursts +system.physmem.perBankRdBursts::11 130505 # Per bank write bursts +system.physmem.perBankRdBursts::12 126282 # Per bank write bursts +system.physmem.perBankRdBursts::13 125429 # Per bank write bursts +system.physmem.perBankRdBursts::14 122618 # Per bank write bursts +system.physmem.perBankRdBursts::15 123223 # Per bank write bursts +system.physmem.perBankWrBursts::0 61508 # Per bank write bursts +system.physmem.perBankWrBursts::1 61766 # Per bank write bursts +system.physmem.perBankWrBursts::2 60822 # Per bank write bursts +system.physmem.perBankWrBursts::3 61512 # Per bank write bursts +system.physmem.perBankWrBursts::4 61965 # Per bank write bursts +system.physmem.perBankWrBursts::5 63432 # Per bank write bursts +system.physmem.perBankWrBursts::6 64483 # Per bank write bursts +system.physmem.perBankWrBursts::7 65996 # Per bank write bursts +system.physmem.perBankWrBursts::8 65772 # Per bank write bursts +system.physmem.perBankWrBursts::9 66160 # Per bank write bursts +system.physmem.perBankWrBursts::10 65806 # Per bank write bursts +system.physmem.perBankWrBursts::11 66084 # Per bank write bursts +system.physmem.perBankWrBursts::12 64700 # Per bank write bursts +system.physmem.perBankWrBursts::13 64663 # Per bank write bursts +system.physmem.perBankWrBursts::14 65022 # Per bank write bursts +system.physmem.perBankWrBursts::15 64589 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 669587587500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1961723 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1024304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241060 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1769781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.933083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.950192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.486388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375005 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271238 15.33% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53445 3.02% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21262 1.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12891 0.73% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6578 0.37% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4909 0.28% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20584 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769781 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.614784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.080179 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59932 99.71% 99.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 127 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 7 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60104 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60104 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.041794 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.999820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.231211 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31815 52.93% 52.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1444 2.40% 55.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21085 35.08% 90.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4727 7.86% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 762 1.27% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 188 0.31% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 35 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 13 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60104 # Writes before turning the bus around for reads +system.physmem.totQLat 40549512750 # Total ticks spent queuing +system.physmem.totMemAccLat 77306919000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9801975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20684.36 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 39434.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.90 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.23 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 792652 # Number of row buffer hits during reads +system.physmem.writeRowHits 422237 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes +system.physmem.avgGap 224240.30 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6484506840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3538173375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379478600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249616320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 304395031755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134738783250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 503519715900 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.985934 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 222173701250 # Time in different power states +system.physmem_0.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 425054234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6895022400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3762165000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7911430800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387718080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43734125760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 311120339490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128839390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 505650192030 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.167712 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212315780250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22358960000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 409349783 # Number of BP lookups +system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282310323 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278567233 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.674122 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 12632 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1004 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11628 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 644930756 # DTB read hits +system.cpu.dtb.read_misses 12159240 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 657089996 # DTB read accesses +system.cpu.dtb.write_hits 218090963 # DTB write hits +system.cpu.dtb.write_misses 7511655 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 225602618 # DTB write accesses +system.cpu.dtb.data_hits 863021719 # DTB hits +system.cpu.dtb.data_misses 19670895 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 882692614 # DTB accesses +system.cpu.itb.fetch_hits 420612911 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 420612948 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 1339175367 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 431750962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3410040939 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409349783 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304740326 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 884658040 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45380368 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420612911 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8286314 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1339100880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546515 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 714090223 53.33% 53.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47658538 3.56% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24213511 1.81% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45104764 3.37% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142790793 10.66% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65948937 4.92% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43596223 3.26% 80.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29427236 2.20% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226270655 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1339100880 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305673 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546374 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353769972 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 403619551 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524217734 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34804152 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22689471 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62026814 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256105292 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2070 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22689471 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372006695 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212568628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537155412 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194673252 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173749438 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1811256 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20472342 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 148588016 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30888023 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371822708 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117670877 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117534302 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136574 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 995619745 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99632674 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717246724 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272457234 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90451892 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58631522 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884174304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 130 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620036143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544818 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148130652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502718906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 101 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1339100880 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.148176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 535608565 40.00% 40.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169639715 12.67% 52.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157955882 11.80% 64.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149207498 11.14% 75.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126008488 9.41% 85.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84159132 6.28% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68020206 5.08% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34099830 2.55% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14401564 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1339100880 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13158046 35.85% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18960543 51.65% 87.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4589272 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716921702 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 112 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896133 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 22 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671538399 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230679552 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2620036143 # Type of FU issued +system.cpu.iq.rate 1.956455 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36707861 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014010 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6615486651 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031199558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518604332 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1939194 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1248781 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886609 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655777108 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 966896 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69396468 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 272651061 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372885 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145563 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111728732 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 286 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6308614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 22689471 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149827283 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21278630 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035173177 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6594541 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717246724 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272457234 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 130 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 801857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20733670 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145563 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10633550 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701156 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19334706 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2574881369 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657090005 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45154774 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 150998743 # number of nop insts executed +system.cpu.iew.exec_refs 882692691 # number of memory reference insts executed +system.cpu.iew.exec_branches 315484112 # Number of branches executed +system.cpu.iew.exec_stores 225602686 # Number of stores executed +system.cpu.iew.exec_rate 1.922737 # Inst execution rate +system.cpu.iew.wb_sent 2549313271 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519490941 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487485532 # num instructions producing a value +system.cpu.iew.wb_consumers 1918368513 # num instructions consuming a value +system.cpu.iew.wb_rate 1.881375 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775391 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 998632615 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15962246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1201120469 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.515069 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 712379439 59.31% 59.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159650119 13.29% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79517213 6.62% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52024602 4.33% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28479101 2.37% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19489140 1.62% 87.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19970906 1.66% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23045357 1.92% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106564592 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1201120469 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1819780126 # Number of instructions committed +system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 605324165 # Number of memory references committed +system.cpu.commit.loads 444595663 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 214632552 # Number of branches committed +system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. +system.cpu.commit.function_calls 16767440 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction +system.cpu.commit.bw_lim_events 106564592 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3827189418 # The number of ROB reads +system.cpu.rob.rob_writes 5774940551 # The number of ROB writes +system.cpu.timesIdled 705 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 74487 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1736043781 # Number of Instructions Simulated +system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.771395 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771395 # CPI: Total CPI of All Threads +system.cpu.ipc 1.296353 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.296353 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463571137 # number of integer regfile reads +system.cpu.int_regfile_writes 2019338951 # number of integer regfile writes +system.cpu.fp_regfile_reads 39668 # number of floating regfile reads +system.cpu.fp_regfile_writes 612 # number of floating regfile writes +system.cpu.misc_regfile_reads 25 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9207202 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211298 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.334011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.451175 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 699 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2968 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498172 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 712346620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712346620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712346620 # number of overall hits +system.cpu.dcache.overall_hits::total 712346620 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12894733 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12894733 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230330 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230330 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 18125063 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18125063 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18125063 # number of overall misses +system.cpu.dcache.overall_misses::total 18125063 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412093066500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315139193599 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 727232260099 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 727232260099 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 727232260099 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 727232260099 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569743181 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569743181 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 730471683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730471683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730471683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730471683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022633 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022633 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032541 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024813 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024813 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40123.019716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40123.019716 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15672953 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9573691 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104455 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks +system.cpu.dcache.writebacks::total 3727750 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5562625 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351141 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3351141 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8913766 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8913766 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8913766 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8913766 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7332108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879189 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879189 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9211297 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211297 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211297 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211297 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84313777567 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84313777567 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267285289067 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267285289067 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 443215.407798 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 753.790798 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.368062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.368062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses +system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 420611422 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 420611422 # number of overall hits +system.cpu.icache.overall_hits::total 420611422 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses +system.cpu.icache.overall_misses::total 1489 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114620499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114620499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114620499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114620499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114620499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114620499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 420612911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 420612911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 420612911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 420612911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 420612911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 420612911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76978.172599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76978.172599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76978.172599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76978.172599 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 274 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79774499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79774499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79774499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79774499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79774499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79774499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 1929018 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958805 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.443396 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.692409 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.438007 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000784 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.519724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958515 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 977 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17550 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106786 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106786 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143738 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6143738 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7250524 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7250524 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7250524 # number of overall hits +system.cpu.l2cache.overall_hits::total 7250524 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 772419 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 772419 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 949 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 949 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1188355 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1188355 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 949 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1960774 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961723 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1960774 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961723 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69313632000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 69313632000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 78342500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 78342500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106514273500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106514273500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 78342500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 175827905500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 175906248000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78342500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 175827905500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 175906248000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3727750 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3727750 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1879205 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 949 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 949 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332093 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7332093 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9211298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9212247 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9211298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9212247 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411035 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.411035 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162076 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162076 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.212866 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.212947 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.212866 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.212947 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89735.793656 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89735.793656 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82552.687039 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82552.687039 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89631.695495 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89631.695495 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks +system.cpu.l2cache.writebacks::total 1024304 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772419 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 772419 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188355 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960774 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961723 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960774 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961723 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61589442000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61589442000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68852500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68852500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94630723500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94630723500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156220165500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156289018000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68852500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156220165500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156289018000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411035 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411035 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162076 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212947 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79735.793656 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79735.793656 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72552.687039 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72552.687039 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79631.695495 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6384166 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332093 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929018 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11141265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000114 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010697 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11139990 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1275 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11141265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12937476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1423999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1189304 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution +system.membus.trans_dist::CleanEvict 903679 # Transaction distribution +system.membus.trans_dist::ReadExReq 772419 # Transaction distribution +system.membus.trans_dist::ReadExResp 772419 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189304 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851429 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851429 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191105728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191105728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3889706 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889706 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3889706 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475680000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 10684396000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index e69de29bb..01aa62af6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -0,0 +1,152 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.913189 # Number of seconds simulated +sim_ticks 913189263000 # Number of ticks simulated +final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1469307 # Simulator instruction rate (inst/s) +host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 737317476 # Simulator tick rate (ticks/s) +host_mem_usage 238516 # Number of bytes of host memory used +host_seconds 1238.53 # Real time elapsed on the host +sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory +system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory +system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory +system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.data_hits 605324165 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 611922547 # DTB accesses +system.cpu.itb.fetch_hits 1826378509 # ITB hits +system.cpu.itb.fetch_misses 18 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1826378527 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 1826378527 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1819780127 # Number of instructions committed +system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_store_insts 162429806 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1826378527 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 214632552 # Number of branches fetched +system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution +system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution +system.membus.trans_dist::WriteReq 160728502 # Transaction distribution +system.membus.trans_dist::WriteResp 160728502 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram +system.membus.snoop_fanout::mean 0.751070 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432393 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 605324165 24.89% 24.89% # Request fanout histogram +system.membus.snoop_fanout::1 1826378509 75.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2431702674 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index e69de29bb..e31f2fa37 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -0,0 +1,543 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.636720 # Number of seconds simulated +sim_ticks 2636719559500 # Number of ticks simulated +final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 874013 # Simulator instruction rate (inst/s) +host_op_rate 874013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1266376533 # Simulator tick rate (ticks/s) +host_mem_usage 247480 # Number of bytes of host memory used +host_seconds 2082.10 # Real time elapsed on the host +sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory +system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65405568 # Number of bytes written to this memory +system.physmem.bytes_written::total 65405568 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951440 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 444595663 # DTB read hits +system.cpu.dtb.read_misses 4897078 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 449492741 # DTB read accesses +system.cpu.dtb.write_hits 160728502 # DTB write hits +system.cpu.dtb.write_misses 1701304 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 162429806 # DTB write accesses +system.cpu.dtb.data_hits 605324165 # DTB hits +system.cpu.dtb.data_misses 6598382 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 611922547 # DTB accesses +system.cpu.itb.fetch_hits 1826378510 # ITB hits +system.cpu.itb.fetch_misses 18 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1826378528 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 5273439119 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1819780127 # Number of instructions committed +system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses +system.cpu.num_func_calls 33534877 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls +system.cpu.num_int_insts 1725565901 # number of integer instructions +system.cpu.num_fp_insts 805526 # number of float instructions +system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read +system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written +system.cpu.num_fp_register_reads 357 # number of times the floating registers were read +system.cpu.num_fp_register_writes 345 # number of times the floating registers were written +system.cpu.num_mem_refs 611922547 # number of memory refs +system.cpu.num_load_insts 449492741 # Number of load instructions +system.cpu.num_store_insts 162429806 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5273439119 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 214632552 # Number of branches fetched +system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction +system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction +system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction +system.cpu.op_class::MemRead 449492741 24.61% 91.11% # Class of executed instruction +system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3679426 # number of writebacks +system.cpu.dcache.writebacks::total 3679426 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.icache.tags.replacements 1 # number of replacements +system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits +system.cpu.icache.overall_hits::total 1826377708 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.icache.overall_misses::total 802 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 1919525 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6053359 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7160294 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7160294 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7160294 # number of overall hits +system.cpu.l2cache.overall_hits::total 7160294 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 782385 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782385 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1169055 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1169055 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951440 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1952242 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses +system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414109 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414109 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161865 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214237 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks +system.cpu.l2cache.writebacks::total 1021962 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1169055 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1169055 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951440 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1952242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414109 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1169857 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution +system.membus.trans_dist::CleanEvict 896683 # Transaction distribution +system.membus.trans_dist::ReadExReq 782385 # Transaction distribution +system.membus.trans_dist::ReadExResp 782385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169857 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5823129 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5823129 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3870887 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3870887 # Request fanout histogram +system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index e69de29bb..836b1fb8a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,917 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.116866 # Number of seconds simulated +sim_ticks 1116865668500 # Number of ticks simulated +final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 243832 # Simulator instruction rate (inst/s) +host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176313668 # Simulator tick rate (ticks/s) +host_mem_usage 266900 # Number of bytes of host memory used +host_seconds 6334.54 # Real time elapsed on the host +sim_insts 1544563088 # Number of instructions simulated +sim_ops 1664032481 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.writeReqs 1050123 # Number of write requests accepted +system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue +system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 127279 # Per bank write bursts +system.physmem.perBankRdBursts::1 124661 # Per bank write bursts +system.physmem.perBankRdBursts::2 121601 # Per bank write bursts +system.physmem.perBankRdBursts::3 123656 # Per bank write bursts +system.physmem.perBankRdBursts::4 122620 # Per bank write bursts +system.physmem.perBankRdBursts::5 122679 # Per bank write bursts +system.physmem.perBankRdBursts::6 123247 # Per bank write bursts +system.physmem.perBankRdBursts::7 123770 # Per bank write bursts +system.physmem.perBankRdBursts::8 131396 # Per bank write bursts +system.physmem.perBankRdBursts::9 133511 # Per bank write bursts +system.physmem.perBankRdBursts::10 132081 # Per bank write bursts +system.physmem.perBankRdBursts::11 133308 # Per bank write bursts +system.physmem.perBankRdBursts::12 133249 # Per bank write bursts +system.physmem.perBankRdBursts::13 133362 # Per bank write bursts +system.physmem.perBankRdBursts::14 129309 # Per bank write bursts +system.physmem.perBankRdBursts::15 129555 # Per bank write bursts +system.physmem.perBankWrBursts::0 66136 # Per bank write bursts +system.physmem.perBankWrBursts::1 64410 # Per bank write bursts +system.physmem.perBankWrBursts::2 62576 # Per bank write bursts +system.physmem.perBankWrBursts::3 63006 # Per bank write bursts +system.physmem.perBankWrBursts::4 63000 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64443 # Per bank write bursts +system.physmem.perBankWrBursts::7 65436 # Per bank write bursts +system.physmem.perBankWrBursts::8 67310 # Per bank write bursts +system.physmem.perBankWrBursts::9 67797 # Per bank write bursts +system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::11 67882 # Per bank write bursts +system.physmem.perBankWrBursts::12 67326 # Per bank write bursts +system.physmem.perBankWrBursts::13 67793 # Per bank write bursts +system.physmem.perBankWrBursts::14 66482 # Per bank write bursts +system.physmem.perBankWrBursts::15 65854 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1116865574000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 2046591 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1050123 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads +system.physmem.totQLat 38124700750 # Total ticks spent queuing +system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.39 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing +system.physmem.readRowHits 773341 # Number of row buffer hits during reads +system.physmem.writeRowHits 411895 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes +system.physmem.avgGap 360661.52 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.196952 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.256935 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 239639355 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 2233731337 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1544563088 # Number of instructions committed +system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed +system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.446190 # CPI: cycles per instruction +system.cpu.ipc 0.691472 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction +system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1664032481 # Class of committed instruction +system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221041 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits +system.cpu.dcache.overall_hits::total 624218806 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses +system.cpu.dcache.overall_misses::total 9589474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks +system.cpu.dcache.writebacks::total 3684567 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency +system.cpu.icache.tags.replacements 29 # number of replacements +system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits +system.cpu.icache.overall_hits::total 465281510 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses +system.cpu.icache.overall_misses::total 819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 29 # number of writebacks +system.cpu.icache.writebacks::total 29 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 2013919 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7179324 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7179360 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits +system.cpu.l2cache.overall_hits::total 7179360 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 801159 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2045813 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses +system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59945000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 179138607000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59945000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 29 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890853 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890853 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334284 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7334284 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9225137 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9225956 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9225137 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9225956 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks +system.cpu.l2cache.writebacks::total 1050123 # number of writebacks +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2013919 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1245432 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution +system.membus.trans_dist::CleanEvict 962724 # Transaction distribution +system.membus.trans_dist::ReadExReq 801159 # Transaction distribution +system.membus.trans_dist::ReadExResp 801159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4059438 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4059438 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index e69de29bb..94c50de3e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1237 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.767804 # Number of seconds simulated +sim_ticks 767803843500 # Number of ticks simulated +final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 196848 # Simulator instruction rate (inst/s) +host_op_rate 212074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 97853290 # Simulator tick rate (ticks/s) +host_mem_usage 309012 # Number of bytes of host memory used +host_seconds 7846.48 # Real time elapsed on the host +sim_insts 1544563024 # Number of instructions simulated +sim_ops 1664032416 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory +system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory +system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673385 # Number of read requests accepted +system.physmem.writeReqs 1635896 # Number of write requests accepted +system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue +system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 301126 # Per bank write bursts +system.physmem.perBankRdBursts::1 298685 # Per bank write bursts +system.physmem.perBankRdBursts::2 284250 # Per bank write bursts +system.physmem.perBankRdBursts::3 287696 # Per bank write bursts +system.physmem.perBankRdBursts::4 287908 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 280645 # Per bank write bursts +system.physmem.perBankRdBursts::7 277366 # Per bank write bursts +system.physmem.perBankRdBursts::8 293768 # Per bank write bursts +system.physmem.perBankRdBursts::9 299240 # Per bank write bursts +system.physmem.perBankRdBursts::10 292091 # Per bank write bursts +system.physmem.perBankRdBursts::11 297828 # Per bank write bursts +system.physmem.perBankRdBursts::12 299005 # Per bank write bursts +system.physmem.perBankRdBursts::13 298032 # Per bank write bursts +system.physmem.perBankRdBursts::14 293386 # Per bank write bursts +system.physmem.perBankRdBursts::15 288652 # Per bank write bursts +system.physmem.perBankWrBursts::0 103980 # Per bank write bursts +system.physmem.perBankWrBursts::1 101811 # Per bank write bursts +system.physmem.perBankWrBursts::2 99205 # Per bank write bursts +system.physmem.perBankWrBursts::3 99712 # Per bank write bursts +system.physmem.perBankWrBursts::4 99000 # Per bank write bursts +system.physmem.perBankWrBursts::5 99026 # Per bank write bursts +system.physmem.perBankWrBursts::6 102693 # Per bank write bursts +system.physmem.perBankWrBursts::7 104157 # Per bank write bursts +system.physmem.perBankWrBursts::8 105172 # Per bank write bursts +system.physmem.perBankWrBursts::9 104159 # Per bank write bursts +system.physmem.perBankWrBursts::10 102137 # Per bank write bursts +system.physmem.perBankWrBursts::11 102620 # Per bank write bursts +system.physmem.perBankWrBursts::12 102863 # Per bank write bursts +system.physmem.perBankWrBursts::13 102594 # Per bank write bursts +system.physmem.perBankWrBursts::14 104213 # Per bank write bursts +system.physmem.perBankWrBursts::15 102497 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 767803802500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 4673385 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1635896 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads +system.physmem.totQLat 128478496877 # Total ticks spent queuing +system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 4.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 1710736 # Number of row buffer hits during reads +system.physmem.writeRowHits 347188 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes +system.physmem.avgGap 121694.34 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.947771 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states +system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.363055 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states +system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 286292198 # Number of BP lookups +system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 1535607688 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 174 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued +system.cpu.iq.rate 1.209614 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 146 # number of nop insts executed +system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542687 # Number of branches executed +system.cpu.iew.exec_stores 181751910 # Number of stores executed +system.cpu.iew.exec_rate 1.190295 # Inst execution rate +system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169207800 # num instructions producing a value +system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563042 # Number of instructions committed +system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 633153379 # Number of memory references committed +system.cpu.commit.loads 458306334 # Number of loads committed +system.cpu.commit.membars 62 # Number of memory barriers committed +system.cpu.commit.branches 213462427 # Number of branches committed +system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. +system.cpu.commit.function_calls 13665177 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction +system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360114616 # The number of ROB reads +system.cpu.rob.rob_writes 3883791528 # The number of ROB writes +system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563024 # Number of Instructions Simulated +system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads +system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 54 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads +system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes +system.cpu.misc_regfile_reads 675853693 # number of misc regfile reads +system.cpu.misc_regfile_writes 124 # number of misc regfile writes +system.cpu.dcache.tags.replacements 17003710 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits +system.cpu.dcache.overall_hits::total 638076218 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses +system.cpu.dcache.overall_misses::total 21285744 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks +system.cpu.dcache.writebacks::total 17003710 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency +system.cpu.icache.tags.replacements 589 # number of replacements +system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits +system.cpu.icache.overall_hits::total 656966815 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses +system.cpu.icache.overall_misses::total 1620 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 589 # number of writebacks +system.cpu.icache.writebacks::total 589 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4706089 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits +system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses +system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks +system.cpu.l2cache.writebacks::total 1635896 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3696594 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 976790 # Transaction distribution +system.membus.trans_dist::ReadExResp 976790 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 9311100 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 9311100 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index e69de29bb..f7caf50c2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -0,0 +1,243 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.832017 # Number of seconds simulated +sim_ticks 832017490500 # Number of ticks simulated +final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1043463 # Simulator instruction rate (inst/s) +host_op_rate 1124173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 562087533 # Simulator tick rate (ticks/s) +host_mem_usage 256656 # Number of bytes of host memory used +host_seconds 1480.23 # Real time elapsed on the host +sim_insts 1544563042 # Number of instructions simulated +sim_ops 1664032434 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory +system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory +system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory +system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 1664034982 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1544563042 # Number of instructions committed +system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions +system.cpu.num_store_insts 174847046 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 213462427 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution +system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution +system.membus.trans_dist::WriteReq 172586047 # Transaction distribution +system.membus.trans_dist::WriteResp 172586047 # Transaction distribution +system.membus.trans_dist::SoftPFReq 1 # Transaction distribution +system.membus.trans_dist::SoftPFResp 1 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondReq 61 # Transaction distribution +system.membus.trans_dist::StoreCondResp 61 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram +system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 2172060895 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e69de29bb..6f79ed44a 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,655 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.377030 # Number of seconds simulated +sim_ticks 2377029670500 # Number of ticks simulated +final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 651336 # Simulator instruction rate (inst/s) +host_op_rate 701905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1006163929 # Simulator tick rate (ticks/s) +host_mem_usage 265624 # Number of bytes of host memory used +host_seconds 2362.47 # Real time elapsed on the host +sim_insts 1538759602 # Number of instructions simulated +sim_ops 1658228915 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory +system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 4754059341 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1538759602 # Number of instructions committed +system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses +system.cpu.num_func_calls 27330256 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls +system.cpu.num_int_insts 1477900422 # number of integer instructions +system.cpu.num_fp_insts 36 # number of float instructions +system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read +system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written +system.cpu.num_fp_register_reads 24 # number of times the floating registers were read +system.cpu.num_fp_register_writes 16 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read +system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written +system.cpu.num_mem_refs 633153380 # number of memory refs +system.cpu.num_load_insts 458306334 # Number of load instructions +system.cpu.num_store_insts 174847046 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 213462427 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction +system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction +system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction +system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1664032481 # Class of executed instruction +system.cpu.dcache.tags.replacements 9111140 # number of replacements +system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits +system.cpu.dcache.overall_hits::total 618379947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses +system.cpu.dcache.overall_misses::total 9115236 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3681379 # number of writebacks +system.cpu.dcache.writebacks::total 3681379 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency +system.cpu.icache.tags.replacements 7 # number of replacements +system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits +system.cpu.icache.overall_hits::total 1544564953 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses +system.cpu.icache.overall_misses::total 638 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 7 # number of writebacks +system.cpu.icache.writebacks::total 7 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 1919027 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits +system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses +system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 638 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7226087 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7226087 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks +system.cpu.l2cache.writebacks::total 1021127 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1169580 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897056 # Transaction distribution +system.membus.trans_dist::ReadExReq 782134 # Transaction distribution +system.membus.trans_dist::ReadExResp 782134 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3869897 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3869897 # Request fanout histogram +system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index e69de29bb..65376a235 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -0,0 +1,127 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.846007 # Number of seconds simulated +sim_ticks 2846007227500 # Number of ticks simulated +final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 786137 # Simulator instruction rate (inst/s) +host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 743780816 # Simulator tick rate (ticks/s) +host_mem_usage 258352 # Number of bytes of host memory used +host_seconds 3826.41 # Real time elapsed on the host +sim_insts 3008081022 # Number of instructions simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory +system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory +system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 5692014456 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 3008081022 # Number of instructions committed +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 33534539 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls +system.cpu.num_int_insts 4684368009 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions +system.cpu.num_store_insts 438528338 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 248500691 # Number of branches fetched +system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction +system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction +system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution +system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution +system.membus.trans_dist::WriteReq 438528338 # Transaction distribution +system.membus.trans_dist::WriteResp 438528338 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram +system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram +system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 5690945966 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e69de29bb..e4e1963fc 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 5.895948 # Number of seconds simulated +sim_ticks 5895947852500 # Number of ticks simulated +final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 545612 # Simulator instruction rate (inst/s) +host_op_rate 850113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1069419451 # Simulator tick rate (ticks/s) +host_mem_usage 268340 # Number of bytes of host memory used +host_seconds 5513.22 # Real time elapsed on the host +sim_insts 3008081022 # Number of instructions simulated +sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory +system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory +system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.numCycles 11791895705 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 3008081022 # Number of instructions committed +system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 33534539 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls +system.cpu.num_int_insts 4684368009 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written +system.cpu.num_mem_refs 1677713084 # number of memory refs +system.cpu.num_load_insts 1239184746 # Number of load instructions +system.cpu.num_store_insts 438528338 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 248500691 # Number of branches fetched +system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction +system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction +system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses +system.cpu.dcache.overall_misses::total 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks +system.cpu.dcache.writebacks::total 3682716 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.icache.tags.replacements 10 # number of replacements +system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4013232207 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4013232207 # number of overall hits +system.cpu.icache.overall_hits::total 4013232207 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.icache.overall_misses::total 675 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4013232882 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4013232882 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4013232882 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 10 # number of writebacks +system.cpu.icache.writebacks::total 10 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 1919169 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits +system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses +system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 675 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222850 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7222850 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks +system.cpu.l2cache.writebacks::total 1022289 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919169 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1169437 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution +system.membus.trans_dist::CleanEvict 896090 # Transaction distribution +system.membus.trans_dist::ReadExReq 782433 # Transaction distribution +system.membus.trans_dist::ReadExResp 782433 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3870249 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3870249 # Request fanout histogram +system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index e69de29bb..05e39f173 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -0,0 +1,764 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.051906 # Number of seconds simulated +sim_ticks 51905634500 # Number of ticks simulated +final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 261291 # Simulator instruction rate (inst/s) +host_op_rate 261291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147573427 # Simulator tick rate (ticks/s) +host_mem_usage 252408 # Number of bytes of host memory used +host_seconds 351.73 # Real time elapsed on the host +sim_insts 91903089 # Number of instructions simulated +sim_ops 91903089 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory +system.physmem.bytes_read::total 340480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3907399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2652198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6559596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3907399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3907399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2652198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6559596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5320 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::1 295 # Per bank write bursts +system.physmem.perBankRdBursts::2 308 # Per bank write bursts +system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::4 224 # Per bank write bursts +system.physmem.perBankRdBursts::5 238 # Per bank write bursts +system.physmem.perBankRdBursts::6 222 # Per bank write bursts +system.physmem.perBankRdBursts::7 289 # Per bank write bursts +system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::9 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 254 # Per bank write bursts +system.physmem.perBankRdBursts::11 261 # Per bank write bursts +system.physmem.perBankRdBursts::12 410 # Per bank write bursts +system.physmem.perBankRdBursts::13 344 # Per bank write bursts +system.physmem.perBankRdBursts::14 500 # Per bank write bursts +system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 51905547000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5320 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 982 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.395112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.989816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.326928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 308 31.36% 31.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 213 21.69% 53.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 101 10.29% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 9.16% 72.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.23% 79.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 3.77% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 21 2.14% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 2.95% 88.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 112 11.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 982 # Bytes accessed per row activation +system.physmem.totQLat 32661000 # Total ticks spent queuing +system.physmem.totMemAccLat 132411000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6139.29 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 24889.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4334 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9756681.77 # Average gap between requests +system.physmem.pageHitRate 81.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3515400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1918125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19983600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1736098875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619147750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770724710 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.912241 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49270880000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 899376250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3885840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2120250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21309600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1812535875 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29552097750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34782010275 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.129676 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49159142250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 11440185 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6076858 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5316207 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 87.482824 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173724 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26312 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 24255 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2057 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20416195 # DTB read hits +system.cpu.dtb.read_misses 43360 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20459555 # DTB read accesses +system.cpu.dtb.write_hits 6579893 # DTB write hits +system.cpu.dtb.write_misses 278 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6580171 # DTB write accesses +system.cpu.dtb.data_hits 26996088 # DTB hits +system.cpu.dtb.data_misses 43638 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 27039726 # DTB accesses +system.cpu.itb.fetch_hits 22951506 # ITB hits +system.cpu.itb.fetch_misses 90 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 22951596 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 103811269 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903089 # Number of instructions committed +system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2181586 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.129573 # CPI: cycles per instruction +system.cpu.ipc 0.885290 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction +system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.op_class_0::MemRead 19996208 21.76% 92.93% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6501126 7.07% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 91903089 # Class of committed instruction +system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.885202 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.414267 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26572424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26572424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26572424 # number of overall hits +system.cpu.dcache.overall_hits::total 26572424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2908 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2908 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3429 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3429 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3429 # number of overall misses +system.cpu.dcache.overall_misses::total 3429 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40464500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40464500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214055500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214055500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254520000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254520000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254520000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20074750 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20074750 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26575853 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26575853 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26575853 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26575853 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000447 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74225.721785 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1163 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1163 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1199 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1199 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1199 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36953000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168350000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168350000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168350000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.icache.tags.replacements 13853 # number of replacements +system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15818 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1449.973891 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1642.330146 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801919 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801919 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 672 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22935687 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22935687 # number of overall hits +system.cpu.icache.overall_hits::total 22935687 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15819 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15819 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15819 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15819 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15819 # number of overall misses +system.cpu.icache.overall_misses::total 15819 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 406827000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 406827000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 406827000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 406827000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 406827000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22951506 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22951506 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22951506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22951506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22951506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25717.618054 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 13853 # number of writebacks +system.cpu.icache.writebacks::total 13853 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15819 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15819 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15819 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15819 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15819 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15819 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 391009000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 391009000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 391009000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 391009000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 391009000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 391009000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3667 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.259067 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.780381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.965355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 359.965124 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3667 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13853 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12649 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12649 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12649 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 12728 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12649 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits +system.cpu.l2cache.overall_hits::total 12728 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3169 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3169 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5320 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses +system.cpu.l2cache.overall_misses::total 5320 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128506000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128506000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234465500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 234465500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35663000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 35663000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234465500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164169000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 398634500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234465500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164169000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 398634500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13853 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13853 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15818 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15818 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15818 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 18048 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15818 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 18048 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200341 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200341 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200341 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.294770 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200341 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.294770 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3169 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111316000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202775500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31343000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202775500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 142659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 345434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202775500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 142659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 345434500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200341 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294770 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200341 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294770 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 32058 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15818 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18048 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18048 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29989000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23727000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3601 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5320 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5320 # Request fanout histogram +system.membus.reqLayer0.occupancy 6419000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 28167750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index e69de29bb..685087aff 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -0,0 +1,1035 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.021909 # Number of seconds simulated +sim_ticks 21909208500 # Number of ticks simulated +final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 161119 # Simulator instruction rate (inst/s) +host_op_rate 161119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41933875 # Simulator tick rate (ticks/s) +host_mem_usage 253948 # Number of bytes of host memory used +host_seconds 522.47 # Real time elapsed on the host +sim_insts 84179709 # Number of instructions simulated +sim_ops 84179709 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8944550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6324281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15268831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8944550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8944550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6324281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15268831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5227 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5227 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 334528 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 334528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 470 # Per bank write bursts +system.physmem.perBankRdBursts::1 291 # Per bank write bursts +system.physmem.perBankRdBursts::2 302 # Per bank write bursts +system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 223 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts +system.physmem.perBankRdBursts::8 239 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts +system.physmem.perBankRdBursts::11 251 # Per bank write bursts +system.physmem.perBankRdBursts::12 395 # Per bank write bursts +system.physmem.perBankRdBursts::13 339 # Per bank write bursts +system.physmem.perBankRdBursts::14 492 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 21909113500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5227 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.435239 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.348968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.138574 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 246 28.70% 28.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 21.70% 50.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 85 9.92% 60.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 7.58% 67.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 37 4.32% 72.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 35 4.08% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 3.97% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 49 5.72% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 120 14.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 857 # Bytes accessed per row activation +system.physmem.totQLat 42496500 # Total ticks spent queuing +system.physmem.totMemAccLat 140502750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8130.19 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26880.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4359 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 4191527.36 # Average gap between requests +system.physmem.pageHitRate 83.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3076920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1678875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19468800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 930163050 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12325856250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14710823175 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.635656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20502630500 # Time in different power states +system.physmem_0.memoryStateTime::REF 731380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 668984500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20771400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1430579280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 904676355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12348213000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14709404805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.570899 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20540502500 # Time in different power states +system.physmem_1.memoryStateTime::REF 731380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 16102191 # Number of BP lookups +system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8963309 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7508263 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.766642 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1594548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 465 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 29370 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3646 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 24064579 # DTB read hits +system.cpu.dtb.read_misses 206327 # DTB read misses +system.cpu.dtb.read_acv 4 # DTB read access violations +system.cpu.dtb.read_accesses 24270906 # DTB read accesses +system.cpu.dtb.write_hits 7168860 # DTB write hits +system.cpu.dtb.write_misses 1193 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7170053 # DTB write accesses +system.cpu.dtb.data_hits 31233439 # DTB hits +system.cpu.dtb.data_misses 207520 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 31440959 # DTB accesses +system.cpu.itb.fetch_hits 15932703 # ITB hits +system.cpu.itb.fetch_misses 79 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 15932782 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 43818418 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 16643559 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137979359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16102191 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9128535 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25956071 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1939868 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2614 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15932703 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 367699 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.166672 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19392056 44.51% 44.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2618542 6.01% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1330036 3.05% 53.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1934112 4.44% 58.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3001913 6.89% 64.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1292242 2.97% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1355704 3.11% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 886645 2.03% 73.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11761101 26.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 43572351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367475 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.148890 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12867028 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8206518 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19434084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2106116 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 958605 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2654233 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11853 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132149690 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49712 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 958605 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13986113 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4641138 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20305818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3670280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128777120 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2026790 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1359443 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54939 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94599417 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167333836 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159779688 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7554147 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 26172056 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8271760 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26904379 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8704430 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3459754 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1614105 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111855372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99762873 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119457 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27677581 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21095041 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1530 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43572351 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.289591 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11226739 25.77% 25.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7658694 17.58% 43.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7470474 17.14% 60.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5702469 13.09% 73.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4463101 10.24% 83.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2983064 6.85% 90.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2041659 4.69% 95.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1171062 2.69% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 855089 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43572351 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 483998 20.16% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34928 1.45% 21.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12187 0.51% 22.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1012495 42.17% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 694978 28.95% 93.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 161680 6.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60663003 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2847512 2.85% 64.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2443315 2.45% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314199 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24854808 24.91% 92.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7268585 7.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 99762873 # Type of FU issued +system.cpu.iq.rate 2.276734 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2400804 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024065 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229929463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129921880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89757813 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15688895 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9653551 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7189472 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93781732 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8381938 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1923340 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 6908181 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11335 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 40937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2203327 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 42874 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1494 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 958605 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3611196 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465334 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122779718 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 241439 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26904379 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8704430 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1919 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38387 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 421097 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 40937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034339 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98437326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24271451 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1325547 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 10922427 # number of nop insts executed +system.cpu.iew.exec_refs 31441543 # number of memory reference insts executed +system.cpu.iew.exec_branches 12471856 # Number of branches executed +system.cpu.iew.exec_stores 7170092 # Number of stores executed +system.cpu.iew.exec_rate 2.246483 # Inst execution rate +system.cpu.iew.wb_sent 97646069 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96947285 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66976790 # num instructions producing a value +system.cpu.iew.wb_consumers 94960923 # num instructions consuming a value +system.cpu.iew.wb_rate 2.212478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705309 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 30878414 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 919665 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39078577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.351750 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.919984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14680368 37.57% 37.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8532696 21.83% 59.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3879932 9.93% 69.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1909819 4.89% 74.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1376650 3.52% 77.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1035169 2.65% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692226 1.77% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 728499 1.86% 84.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6243218 15.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39078577 # Number of insts commited each cycle +system.cpu.commit.committedInsts 91903055 # Number of instructions committed +system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 26497301 # Number of memory references committed +system.cpu.commit.loads 19996198 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 10240685 # Number of branches committed +system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. +system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. +system.cpu.commit.function_calls 1029620 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 19996198 21.76% 92.93% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction +system.cpu.commit.bw_lim_events 6243218 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155615788 # The number of ROB reads +system.cpu.rob.rob_writes 250112160 # The number of ROB writes +system.cpu.timesIdled 4756 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 246067 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 84179709 # Number of Instructions Simulated +system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.520534 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520534 # CPI: Total CPI of All Threads +system.cpu.ipc 1.921103 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.921103 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133011224 # number of integer regfile reads +system.cpu.int_regfile_writes 72905073 # number of integer regfile writes +system.cpu.fp_regfile_reads 6263399 # number of floating regfile reads +system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes +system.cpu.misc_regfile_reads 719113 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12734.411136 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.375474 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355805 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 536 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492632 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28588283 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28588283 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28588283 # number of overall hits +system.cpu.dcache.overall_hits::total 28588283 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1074 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1074 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8471 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8471 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 9545 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9545 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9545 # number of overall misses +system.cpu.dcache.overall_misses::total 9545 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71413000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71413000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 546757246 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 546757246 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 618170246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 618170246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 618170246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22096725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28597828 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28597828 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28597828 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28597828 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001303 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64763.776427 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32543 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 392 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.017857 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 559 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 559 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6742 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6742 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1729 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39779500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39779500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135885995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135885995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175665495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175665495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175665495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.icache.tags.replacements 9515 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11453 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1389.880119 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.928709 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781703 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15918297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15918297 # number of overall hits +system.cpu.icache.overall_hits::total 15918297 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14405 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14405 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14405 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14405 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14405 # number of overall misses +system.cpu.icache.overall_misses::total 14405 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446574000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446574000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446574000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446574000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446574000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446574000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15932702 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15932702 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15932702 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15932702 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15932702 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15932702 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000904 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000904 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000904 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000904 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000904 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000904 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31001.318986 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 31001.318986 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 31001.318986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 31001.318986 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 31001.318986 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 9515 # number of writebacks +system.cpu.icache.writebacks::total 9515 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2951 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2951 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2951 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2951 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2951 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11454 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11454 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11454 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11454 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11454 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11454 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 336702000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 336702000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 336702000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 336702000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 336702000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 336702000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3589 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.022848 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.652891 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.506649 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 381.204708 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011633 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 909 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9515 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8392 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8392 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 54 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 54 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8392 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8472 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8392 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits +system.cpu.l2cache.overall_hits::total 8472 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1703 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1703 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3062 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3062 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 462 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 462 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3062 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5227 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3062 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses +system.cpu.l2cache.overall_misses::total 5227 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132876500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 132876500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 231097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 231097000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38506000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38506000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 231097000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 171382500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 402479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 231097000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 171382500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 402479500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9515 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9515 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1729 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1729 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11454 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11454 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 516 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13699 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 13699 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.984962 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267330 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267330 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.895349 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.895349 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267330 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.381561 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267330 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.381561 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3062 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3062 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5227 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115846500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200477000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33886000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 149732500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350209500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 149732500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350209500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267330 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.381561 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267330 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.381561 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 23372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32422 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 37070 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1492544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13699 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13699 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13699 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21309000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 3524 # Transaction distribution +system.membus.trans_dist::ReadExReq 1703 # Transaction distribution +system.membus.trans_dist::ReadExResp 1703 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3524 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10454 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5227 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5227 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5227 # Request fanout histogram +system.membus.reqLayer0.occupancy 6276500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 27456000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index e69de29bb..28e1374ff 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -0,0 +1,882 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.130383 # Number of seconds simulated +sim_ticks 130382890500 # Number of ticks simulated +final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 181123 # Simulator instruction rate (inst/s) +host_op_rate 190933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137045131 # Simulator tick rate (ticks/s) +host_mem_usage 270196 # Number of bytes of host memory used +host_seconds 951.39 # Real time elapsed on the host +sim_insts 172317810 # Number of instructions simulated +sim_ops 181650743 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory +system.physmem.bytes_read::total 247424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3866 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 305 # Per bank write bursts +system.physmem.perBankRdBursts::1 217 # Per bank write bursts +system.physmem.perBankRdBursts::2 135 # Per bank write bursts +system.physmem.perBankRdBursts::3 313 # Per bank write bursts +system.physmem.perBankRdBursts::4 306 # Per bank write bursts +system.physmem.perBankRdBursts::5 305 # Per bank write bursts +system.physmem.perBankRdBursts::6 273 # Per bank write bursts +system.physmem.perBankRdBursts::7 222 # Per bank write bursts +system.physmem.perBankRdBursts::8 248 # Per bank write bursts +system.physmem.perBankRdBursts::9 218 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 200 # Per bank write bursts +system.physmem.perBankRdBursts::12 183 # Per bank write bursts +system.physmem.perBankRdBursts::13 218 # Per bank write bursts +system.physmem.perBankRdBursts::14 224 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 130382796000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 3866 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation +system.physmem.totQLat 27071500 # Total ticks spent queuing +system.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.01 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 2948 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 33725503.36 # Average gap between requests +system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.831686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states +system.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.803682 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 49622074 # Number of BP lookups +system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22843202 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 260765781 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 172317810 # Number of instructions committed +system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed +system.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.513284 # CPI: cycles per instruction +system.cpu.ipc 0.660815 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction +system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 181650743 # Class of committed instruction +system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 42 # number of replacements +system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits +system.cpu.dcache.overall_hits::total 40709659 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses +system.cpu.dcache.overall_misses::total 2441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 16 # number of writebacks +system.cpu.dcache.writebacks::total 16 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency +system.cpu.icache.tags.replacements 2881 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses +system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits +system.cpu.icache.overall_hits::total 70779397 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses +system.cpu.icache.overall_misses::total 4678 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 2881 # number of writebacks +system.cpu.icache.writebacks::total 2881 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits +system.cpu.l2cache.overall_hits::total 2606 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses +system.cpu.l2cache.overall_misses::total 3883 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 2775 # Transaction distribution +system.membus.trans_dist::ReadExReq 1091 # Transaction distribution +system.membus.trans_dist::ReadExResp 1091 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3866 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 3866 # Request fanout histogram +system.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e69de29bb..5e6d9ee12 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -0,0 +1,1172 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.084938 # Number of seconds simulated +sim_ticks 84937723500 # Number of ticks simulated +final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 96546 # Simulator instruction rate (inst/s) +host_op_rate 101775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47592642 # Simulator tick rate (ticks/s) +host_mem_usage 268276 # Number of bytes of host memory used +host_seconds 1784.68 # Real time elapsed on the host +sim_insts 172303022 # Number of instructions simulated +sim_ops 181635954 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory +system.physmem.bytes_read::total 790400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12350 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6914807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1555210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9305641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6914807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6914807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1555210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9305641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12351 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 12351 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 790464 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 790464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1113 # Per bank write bursts +system.physmem.perBankRdBursts::1 381 # Per bank write bursts +system.physmem.perBankRdBursts::2 5089 # Per bank write bursts +system.physmem.perBankRdBursts::3 423 # Per bank write bursts +system.physmem.perBankRdBursts::4 1959 # Per bank write bursts +system.physmem.perBankRdBursts::5 424 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 373 # Per bank write bursts +system.physmem.perBankRdBursts::8 266 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 324 # Per bank write bursts +system.physmem.perBankRdBursts::12 199 # Per bank write bursts +system.physmem.perBankRdBursts::13 249 # Per bank write bursts +system.physmem.perBankRdBursts::14 229 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 84937714500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 12351 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 7250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.738207 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.269087 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 131.624325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5249 72.40% 72.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1564 21.57% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 167 2.30% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 93 1.28% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 42 0.58% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 24 0.33% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 0.25% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 0.29% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 0.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7250 # Bytes accessed per row activation +system.physmem.totQLat 171430514 # Total ticks spent queuing +system.physmem.totMemAccLat 403011764 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13879.89 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32629.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 5094 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 41.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 6876990.89 # Average gap between requests +system.physmem.pageHitRate 41.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48452040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26437125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78179400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16645874445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36357960750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 58704276240 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.186004 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60381088491 # Time in different power states +system.physmem_0.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21718991509 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 6335280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3456750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17877600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5547372480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3295031490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48069226500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56939300100 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.405119 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 79958437412 # Time in different power states +system.physmem_1.memoryStateTime::REF 2836080000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 85626366 # Number of BP lookups +system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39946926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38187698 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 95.596087 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3683716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81912 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 681689 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 653746 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 169875448 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 5671940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 347162762 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85626366 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42525160 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 157499775 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11884731 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 3808 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78326624 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.147875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.049260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17456404 10.32% 10.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30071791 17.78% 28.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31598997 18.68% 46.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89993328 53.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 169120520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.504054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.043631 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17509987 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17244874 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121866560 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6731455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5767644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11064434 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189777 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304997911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27240618 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5767644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37477523 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8502539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 578983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108355768 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8438063 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 277420851 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13180734 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3058487 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 843003 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280960 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36243 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27083 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 481449871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1191735135 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296461789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004325 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 188472942 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23603 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23603 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13353784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33915046 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14407100 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2540378 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1803003 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263798584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45955 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214411803 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5187874 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82208585 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 217092419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169120520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.267805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017994 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52408217 30.99% 30.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 35940187 21.25% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65510990 38.74% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13642635 8.07% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570936 0.93% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47343 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169120520 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35659439 66.16% 66.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153265 0.28% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35730 0.07% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 958 0.00% 66.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34286 0.06% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14056522 26.08% 92.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3955910 7.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166992897 77.88% 77.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919175 0.43% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165179 0.08% 78.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245702 0.11% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460499 0.21% 78.77% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206683 0.10% 78.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31868874 14.86% 93.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13371819 6.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 214411803 # Type of FU issued +system.cpu.iq.rate 1.262171 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53897621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251374 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653076785 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344050437 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204251594 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952836 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2009578 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806333 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266175663 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133761 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1598827 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 6018902 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7034 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1762466 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 25527 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 769 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 5767644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5618767 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 62916 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263864756 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 33915046 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14407100 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3855 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 55872 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7034 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3149041 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3246654 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6395695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207125960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30633355 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7285843 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 20217 # number of nop insts executed +system.cpu.iew.exec_refs 43771495 # number of memory reference insts executed +system.cpu.iew.exec_branches 44852998 # Number of branches executed +system.cpu.iew.exec_stores 13138140 # Number of stores executed +system.cpu.iew.exec_rate 1.219281 # Inst execution rate +system.cpu.iew.wb_sent 206368045 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206057927 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129397136 # num instructions producing a value +system.cpu.iew.wb_consumers 221651580 # num instructions consuming a value +system.cpu.iew.wb_rate 1.212994 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68672645 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 5760731 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 157823719 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.150970 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.652577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73232232 46.40% 46.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41142749 26.07% 72.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22534270 14.28% 86.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9514853 6.03% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552076 2.25% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2143258 1.36% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1327703 0.84% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1008942 0.64% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3367636 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 157823719 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172317410 # Number of instructions committed +system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 40540778 # Number of memory references committed +system.cpu.commit.loads 27896144 # Number of loads committed +system.cpu.commit.membars 22408 # Number of memory barriers committed +system.cpu.commit.branches 40300312 # Number of branches committed +system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. +system.cpu.commit.int_insts 143085667 # Number of committed integer instructions. +system.cpu.commit.function_calls 1848934 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction +system.cpu.commit.bw_lim_events 3367636 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 404773869 # The number of ROB reads +system.cpu.rob.rob_writes 511956769 # The number of ROB writes +system.cpu.timesIdled 9030 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 754928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172303022 # Number of Instructions Simulated +system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.985911 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.985911 # CPI: Total CPI of All Threads +system.cpu.ipc 1.014290 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.014290 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218725741 # number of integer regfile reads +system.cpu.int_regfile_writes 114168991 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904222 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441435 # number of floating regfile writes +system.cpu.cc_regfile_reads 708194084 # number of cc regfile reads +system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes +system.cpu.misc_regfile_reads 59249203 # number of misc regfile reads +system.cpu.misc_regfile_writes 820036 # number of misc regfile writes +system.cpu.dcache.tags.replacements 72581 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 561.355766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 508221500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.413915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341311 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 364 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 364 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40986258 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40986258 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40986622 # number of overall hits +system.cpu.dcache.overall_hits::total 40986622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89227 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89227 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22976 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22976 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112203 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112203 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112319 # number of overall misses +system.cpu.dcache.overall_misses::total 112319 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1066843000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241030499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241030499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2297500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307873499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307873499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307873499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28734174 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41098461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41098461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41098941 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41098941 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003105 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.241667 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8870.656371 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11656.314885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11644.276561 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10738 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428241 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72581 # number of writebacks +system.cpu.dcache.writebacks::total 72581 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24802 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24802 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14421 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14421 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39223 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39223 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39223 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8555 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73093 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73093 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 653903000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85317499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 739220499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 740182499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002242 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.235417 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001776 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9972.822794 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency +system.cpu.icache.tags.replacements 53623 # number of replacements +system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54135 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1445.812413 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84183071500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.594536 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 51 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78269055 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78269055 # number of overall hits +system.cpu.icache.overall_hits::total 78269055 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57535 # number of overall misses +system.cpu.icache.overall_misses::total 57535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1155198430 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1155198430 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1155198430 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1155198430 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1155198430 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78326590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78326590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78326590 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78326590 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78326590 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20078.185974 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 73195 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3246 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.549291 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 53623 # number of writebacks +system.cpu.icache.writebacks::total 53623 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3399 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3399 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3399 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3399 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3399 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3399 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54136 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54136 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54136 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54136 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54136 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54136 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1039886452 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1039886452 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1039886452 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1039886452 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000691 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000691 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000691 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3198 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.277986 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1986.257511 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 155.113391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.121232 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.130699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 254 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 856 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1653 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 51033 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8387 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8387 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 44953 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 44953 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 62632 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 62632 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 44953 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 71019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 115972 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 44953 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 71019 # number of overall hits +system.cpu.l2cache.overall_hits::total 115972 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9183 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 9183 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1839 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1839 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9183 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2074 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 11257 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9183 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2074 # number of overall misses +system.cpu.l2cache.overall_misses::total 11257 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18101500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18101500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 689865000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 689865000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 142794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 142794500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 689865000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 160896000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 850761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 689865000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 160896000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 850761000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 64698 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 64698 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 51033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 51033 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8622 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8622 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54136 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 54136 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64471 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64471 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54136 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 127229 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54136 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 127229 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027256 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027256 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.169628 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.169628 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.028524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.028524 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.169628 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.028375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.088478 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.169628 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.028375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.088478 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77027.659574 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77027.659574 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75124.142437 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75124.142437 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77647.906471 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75576.174825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 9 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 9 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2007 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2007 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 234 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 234 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1830 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9178 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2064 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 11242 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9178 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2064 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 13249 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68828649 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16491500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16491500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 634496500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 634496500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 131272000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 131272000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 634496500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147763500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 782260000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 634496500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68828649 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 851088649 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027140 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.169536 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028385 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.088360 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.169536 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.104135 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 253433 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 126224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11007 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8622 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54136 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64471 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380661 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6896512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16219648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13357 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 140586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.219979 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.541213 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 118188 84.07% 84.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13870 9.87% 93.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8528 6.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 140586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 252920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 81207989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 12116 # Transaction distribution +system.membus.trans_dist::ReadExReq 234 # Transaction distribution +system.membus.trans_dist::ReadExResp 234 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12117 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24701 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 790400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 12351 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 12351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 12351 # Request fanout histogram +system.membus.reqLayer0.occupancy 15618188 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 66520835 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index e69de29bb..87cd506ee 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -0,0 +1,1008 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.103324 # Number of seconds simulated +sim_ticks 103324153500 # Number of ticks simulated +final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 48808 # Simulator instruction rate (inst/s) +host_op_rate 81806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38183996 # Simulator tick rate (ticks/s) +host_mem_usage 302208 # Number of bytes of host memory used +host_seconds 2705.95 # Real time elapsed on the host +sim_insts 132071192 # Number of instructions simulated +sim_ops 221363384 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory +system.physmem.bytes_read::total 361984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 231488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 231488 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2039 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5656 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2240405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1262977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3503382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2240405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2240405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1262977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3503382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5656 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5656 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 361984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 361984 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 310 # Per bank write bursts +system.physmem.perBankRdBursts::1 382 # Per bank write bursts +system.physmem.perBankRdBursts::2 476 # Per bank write bursts +system.physmem.perBankRdBursts::3 358 # Per bank write bursts +system.physmem.perBankRdBursts::4 362 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 419 # Per bank write bursts +system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::8 389 # Per bank write bursts +system.physmem.perBankRdBursts::9 295 # Per bank write bursts +system.physmem.perBankRdBursts::10 260 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 228 # Per bank write bursts +system.physmem.perBankRdBursts::13 484 # Per bank write bursts +system.physmem.perBankRdBursts::14 420 # Per bank write bursts +system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 103323899000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5656 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4508 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.278481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.439317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.670037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 554 43.83% 43.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 264 20.89% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 8.31% 73.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 69 5.46% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 45 3.56% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 4.51% 86.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.22% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.34% 90.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 125 9.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1264 # Bytes accessed per row activation +system.physmem.totQLat 43672750 # Total ticks spent queuing +system.physmem.totMemAccLat 149722750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7721.49 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26471.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4391 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 18268016.09 # Average gap between requests +system.physmem.pageHitRate 77.63 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5624640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3069000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 23610600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3147948405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59232949500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 69161793345 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.369133 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 98535205500 # Time in different power states +system.physmem_0.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1338454000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3931200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2145000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20490600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6748591200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2964574845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 59393774250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 69133507095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.095685 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 98803806250 # Time in different power states +system.physmem_1.memoryStateTime::REF 3450200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 40908032 # Number of BP lookups +system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 35316490 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3206071 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 604531 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 35316490 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9869044 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.numCycles 206648308 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 46351281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 420030465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40908032 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13075115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 152558958 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14935189 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5881 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 68758 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 764 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 41261989 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1525874 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.416062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.660543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 99211398 48.06% 48.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5135847 2.49% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5374620 2.60% 53.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5328555 2.58% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6013612 2.91% 58.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5856529 2.84% 61.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5733209 2.78% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4747222 2.30% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 69052549 33.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 206453541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197960 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032586 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32305475 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86547165 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 62440790 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17692517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7467594 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 591140753 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7467594 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42099614 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46622929 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68917298 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41316526 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 552365156 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1615 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36415427 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4818042 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 146051 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 629691896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1486514399 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 974943820 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 15152274 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 370262446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2381 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2386 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89347483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 128815998 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45923960 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 77358410 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25275137 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 490566423 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62065 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 338414549 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1099553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 269265104 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527048763 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 60820 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 206453541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.639180 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 73345677 35.53% 35.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46646037 22.59% 58.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32854801 15.91% 74.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20905072 10.13% 84.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15063521 7.30% 91.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8409386 4.07% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5213188 2.53% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2363320 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1652539 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 206453541 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 758238 19.31% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2733075 69.60% 88.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 435620 11.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 1211810 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 216608884 64.01% 64.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 799973 0.24% 64.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048329 2.08% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1813849 0.54% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 84312637 24.91% 92.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26619067 7.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 338414549 # Type of FU issued +system.cpu.iq.rate 1.637635 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3926933 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 880106724 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 745207821 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 316030450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8202401 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15512263 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3567674 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 337013730 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4115942 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18154732 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 72166411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 54986 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 863760 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25408243 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 50543 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 7467594 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35770303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 592137 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 490628488 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1259959 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 128815998 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45923960 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22654 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 545800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38626 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 863760 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1294864 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6880130 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8174994 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 326485130 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80685795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11929419 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 106318426 # number of memory reference insts executed +system.cpu.iew.exec_branches 18939296 # Number of branches executed +system.cpu.iew.exec_stores 25632631 # Number of stores executed +system.cpu.iew.exec_rate 1.579907 # Inst execution rate +system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back +system.cpu.iew.wb_producers 256503247 # num instructions producing a value +system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value +system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle +system.cpu.commit.committedInsts 132071192 # Number of instructions committed +system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 77165304 # Number of memory references committed +system.cpu.commit.loads 56649587 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 12326938 # Number of branches committed +system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. +system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. +system.cpu.commit.function_calls 797818 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction +system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 647577665 # The number of ROB reads +system.cpu.rob.rob_writes 1024269930 # The number of ROB writes +system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 132071192 # Number of Instructions Simulated +system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads +system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 524516370 # number of integer regfile reads +system.cpu.int_regfile_writes 289029189 # number of integer regfile writes +system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads +system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes +system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads +system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes +system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads +system.cpu.misc_regfile_writes 1689 # number of misc regfile writes +system.cpu.dcache.tags.replacements 72 # number of replacements +system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits +system.cpu.dcache.overall_hits::total 82765643 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses +system.cpu.dcache.overall_misses::total 3286 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.icache.tags.replacements 6515 # number of replacements +system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses +system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits +system.cpu.icache.overall_hits::total 41248897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses +system.cpu.icache.overall_misses::total 13089 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 6515 # number of writebacks +system.cpu.icache.writebacks::total 6515 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 68 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 68 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 74 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 74 # number of overall hits +system.cpu.l2cache.overall_hits::total 4951 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 500 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 500 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3617 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3617 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3617 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2039 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5656 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3617 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2039 # number of overall misses +system.cpu.l2cache.overall_misses::total 5656 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 112056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 112056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275028000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 275028000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45953000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 45953000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 275028000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 158009000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 433037000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 275028000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 158009000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 433037000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 18 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 18 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6469 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1513 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1513 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8494 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 600 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 600 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8494 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2113 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10607 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8494 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2113 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10607 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990099 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990099 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996034 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.996034 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.425830 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.425830 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886667 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886667 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.425830 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964979 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.533233 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.425830 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964979 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.533233 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3617 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2039 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3617 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2039 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5656 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 9503500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 9503500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 96986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 96986000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 238858000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 238858000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40633000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40633000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238858000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 376477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 507 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11619 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.094328 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.292297 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10523 90.57% 90.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1096 9.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 11619 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15636499 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 13500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4149 # Transaction distribution +system.membus.trans_dist::UpgradeReq 500 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4149 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 361984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6156 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 6156 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 6156 # Request fanout histogram +system.membus.reqLayer0.occupancy 7649501 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 30011250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |