diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
| commit | de489e1997ee6c37aaf6e876e32622f6c648fe95 (patch) | |
| tree | 40d4093453491b007167c971ebbb18c8ae0b77fa /tests/long | |
| parent | 08cec03f8ec3bc427700343a7bd7d216433f93fc (diff) | |
| download | gem5-de489e1997ee6c37aaf6e876e32622f6c648fe95.tar.xz | |
stats: updates due to recent chagnesets
Diffstat (limited to 'tests/long')
3 files changed, 2900 insertions, 2901 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index a204e1584..41332b402 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.152315 # Number of seconds simulated -sim_ticks 5152314519000 # Number of ticks simulated -final_tick 5152314519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.152314 # Number of seconds simulated +sim_ticks 5152313559000 # Number of ticks simulated +final_tick 5152313559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171705 # Simulator instruction rate (inst/s) -host_op_rate 339400 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2173929918 # Simulator tick rate (ticks/s) -host_mem_usage 815744 # Number of bytes of host memory used -host_seconds 2370.05 # Real time elapsed on the host -sim_insts 406948645 # Number of instructions simulated -sim_ops 804394656 # Number of ops (including micro ops) simulated +host_inst_rate 122296 # Simulator instruction rate (inst/s) +host_op_rate 241737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1548372689 # Simulator tick rate (ticks/s) +host_mem_usage 812680 # Number of bytes of host memory used +host_seconds 3327.57 # Real time elapsed on the host +sim_insts 406949634 # Number of instructions simulated +sim_ops 804396566 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1035840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10724032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1035776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10724352 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11792640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1035840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1035840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9542144 # Number of bytes written to this memory -system.physmem.bytes_written::total 9542144 # Number of bytes written to this memory +system.physmem.bytes_read::total 11792896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1035776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9542784 # Number of bytes written to this memory +system.physmem.bytes_written::total 9542784 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167568 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 184260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149096 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149096 # Number of write requests responded to by this memory +system.physmem.num_reads::total 184264 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149106 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149106 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2081401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2081463 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2288804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1852011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1852011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1852011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2288854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852136 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852136 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2081401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2081463 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4140816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184260 # Number of read requests accepted -system.physmem.writeReqs 149096 # Number of write requests accepted -system.physmem.readBursts 184260 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149096 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11779776 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12864 # Total number of bytes read from write queue -system.physmem.bytesWritten 9541120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11792640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9542144 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 201 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 4140990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184264 # Number of read requests accepted +system.physmem.writeReqs 149106 # Number of write requests accepted +system.physmem.readBursts 184264 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149106 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11780160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12736 # Total number of bytes read from write queue +system.physmem.bytesWritten 9541632 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11792896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9542784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 199 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 58140 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11261 # Per bank write bursts -system.physmem.perBankRdBursts::1 10600 # Per bank write bursts -system.physmem.perBankRdBursts::2 12322 # Per bank write bursts -system.physmem.perBankRdBursts::3 11592 # Per bank write bursts -system.physmem.perBankRdBursts::4 11482 # Per bank write bursts -system.physmem.perBankRdBursts::5 10950 # Per bank write bursts -system.physmem.perBankRdBursts::6 11082 # Per bank write bursts -system.physmem.perBankRdBursts::7 11124 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 58128 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11264 # Per bank write bursts +system.physmem.perBankRdBursts::1 10595 # Per bank write bursts +system.physmem.perBankRdBursts::2 12318 # Per bank write bursts +system.physmem.perBankRdBursts::3 11595 # Per bank write bursts +system.physmem.perBankRdBursts::4 11491 # Per bank write bursts +system.physmem.perBankRdBursts::5 10948 # Per bank write bursts +system.physmem.perBankRdBursts::6 11084 # Per bank write bursts +system.physmem.perBankRdBursts::7 11123 # Per bank write bursts system.physmem.perBankRdBursts::8 10622 # Per bank write bursts -system.physmem.perBankRdBursts::9 11032 # Per bank write bursts +system.physmem.perBankRdBursts::9 11029 # Per bank write bursts system.physmem.perBankRdBursts::10 11540 # Per bank write bursts -system.physmem.perBankRdBursts::11 11373 # Per bank write bursts +system.physmem.perBankRdBursts::11 11371 # Per bank write bursts system.physmem.perBankRdBursts::12 12384 # Per bank write bursts -system.physmem.perBankRdBursts::13 12480 # Per bank write bursts -system.physmem.perBankRdBursts::14 11990 # Per bank write bursts +system.physmem.perBankRdBursts::13 12484 # Per bank write bursts +system.physmem.perBankRdBursts::14 11992 # Per bank write bursts system.physmem.perBankRdBursts::15 12225 # Per bank write bursts -system.physmem.perBankWrBursts::0 9586 # Per bank write bursts -system.physmem.perBankWrBursts::1 9015 # Per bank write bursts -system.physmem.perBankWrBursts::2 9694 # Per bank write bursts -system.physmem.perBankWrBursts::3 9483 # Per bank write bursts -system.physmem.perBankWrBursts::4 9592 # Per bank write bursts -system.physmem.perBankWrBursts::5 9320 # Per bank write bursts -system.physmem.perBankWrBursts::6 9057 # Per bank write bursts -system.physmem.perBankWrBursts::7 9053 # Per bank write bursts +system.physmem.perBankWrBursts::0 9588 # Per bank write bursts +system.physmem.perBankWrBursts::1 9011 # Per bank write bursts +system.physmem.perBankWrBursts::2 9691 # Per bank write bursts +system.physmem.perBankWrBursts::3 9485 # Per bank write bursts +system.physmem.perBankWrBursts::4 9599 # Per bank write bursts +system.physmem.perBankWrBursts::5 9316 # Per bank write bursts +system.physmem.perBankWrBursts::6 9059 # Per bank write bursts +system.physmem.perBankWrBursts::7 9052 # Per bank write bursts system.physmem.perBankWrBursts::8 8752 # Per bank write bursts -system.physmem.perBankWrBursts::9 9410 # Per bank write bursts +system.physmem.perBankWrBursts::9 9407 # Per bank write bursts system.physmem.perBankWrBursts::10 9210 # Per bank write bursts -system.physmem.perBankWrBursts::11 8755 # Per bank write bursts -system.physmem.perBankWrBursts::12 9657 # Per bank write bursts -system.physmem.perBankWrBursts::13 9381 # Per bank write bursts -system.physmem.perBankWrBursts::14 9483 # Per bank write bursts -system.physmem.perBankWrBursts::15 9632 # Per bank write bursts +system.physmem.perBankWrBursts::11 8756 # Per bank write bursts +system.physmem.perBankWrBursts::12 9659 # Per bank write bursts +system.physmem.perBankWrBursts::13 9383 # Per bank write bursts +system.physmem.perBankWrBursts::14 9487 # Per bank write bursts +system.physmem.perBankWrBursts::15 9633 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 5152314469500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 5152313509500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184260 # Read request sizes (log2) +system.physmem.readPktSize::6 184264 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149096 # Write request sizes (log2) +system.physmem.writePktSize::6 149106 # Write request sizes (log2) system.physmem.rdQLenPdf::0 169844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 461 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,92 +156,92 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 73146 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.483225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.242867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.005738 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28143 38.48% 38.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17778 24.30% 62.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7759 10.61% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4281 5.85% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2977 4.07% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2397 3.28% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1373 1.88% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1102 1.51% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7336 10.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 73146 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7286 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.261872 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.739811 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7285 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.431727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.195666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.031817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28160 38.49% 38.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17784 24.31% 62.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7754 10.60% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4294 5.87% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2960 4.05% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2393 3.27% 86.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1365 1.87% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1117 1.53% 89.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7335 10.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73162 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7284 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.269357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.815412 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7283 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7286 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7286 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.461158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.651895 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.024155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6243 85.68% 85.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 165 2.26% 87.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 39 0.54% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 177 2.43% 90.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.30% 91.22% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7284 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7284 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.467875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.652190 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.050833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6239 85.65% 85.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 170 2.33% 87.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 40 0.55% 88.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 173 2.38% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.30% 91.21% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 151 2.07% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 106 1.45% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.15% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 24 0.33% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 33 0.45% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.10% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 220 3.02% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 103 1.41% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.14% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.33% 95.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 33 0.45% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.10% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.11% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 223 3.06% 98.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 4 0.05% 98.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 9 0.12% 99.07% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 29 0.40% 99.46% # Writes before turning the bus around for reads @@ -257,13 +257,13 @@ system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Wr system.physmem.wrPerTurnAround::152-155 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7286 # Writes before turning the bus around for reads -system.physmem.totQLat 2105191048 # Total ticks spent queuing -system.physmem.totMemAccLat 5556297298 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 920295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11437.59 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 7284 # Writes before turning the bus around for reads +system.physmem.totQLat 2101117298 # Total ticks spent queuing +system.physmem.totMemAccLat 5552336048 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 920325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11415.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30187.59 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30165.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s @@ -274,143 +274,143 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing -system.physmem.readRowHits 150243 # Number of row buffer hits during reads -system.physmem.writeRowHits 109749 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.readRowHits 150235 # Number of row buffer hits during reads +system.physmem.writeRowHits 109755 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.61 # Row buffer hit rate for writes -system.physmem.avgGap 15455892.41 # Average gap between requests +system.physmem.avgGap 15455240.45 # Average gap between requests system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 269634960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 147122250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 705213600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 484704000 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 269725680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147171750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 705252600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 484710480 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 132970948335 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2974744703250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3445846141035 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.796378 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4948677575724 # Time in different power states +system.physmem_0.actBackEnergy 132965791830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2974749226500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3445845693480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.796291 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4948684136224 # Time in different power states system.physmem_0.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31589843276 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31582322276 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 283348800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 154605000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 730438800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 481334400 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 283379040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 154621500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 730446600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 481379760 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 336523814640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 133265512935 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2974486313250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3445925367825 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.811755 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4948236275986 # Time in different power states +system.physmem_1.actBackEnergy 133234904790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2974513162500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3445921708830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811045 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4948281584736 # Time in different power states system.physmem_1.memoryStateTime::REF 172046940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32026607764 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31981299014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86360408 # Number of BP lookups -system.cpu.branchPred.condPredicted 86360408 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 844738 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79711483 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77808056 # Number of BTB hits +system.cpu.branchPred.lookups 86361942 # Number of BP lookups +system.cpu.branchPred.condPredicted 86361942 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844867 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79712463 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77809670 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.612104 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1540361 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177639 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.612929 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1539914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177576 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465551291 # number of cpu cycles simulated +system.cpu.numCycles 465537238 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27284501 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426653476 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86360408 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79348417 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433446162 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1774418 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 139394 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 62229 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 198576 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27283425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426658175 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86361942 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79349584 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433433945 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1774834 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 138611 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 62197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 198243 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 774 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8943748 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 426371 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8943730 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 426192 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 4516 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 462018901 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.822492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.015475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 462004671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.822565 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.015508 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297432046 64.38% 64.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2127313 0.46% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72010980 15.59% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1540927 0.33% 80.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2092821 0.45% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2281981 0.49% 81.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1471602 0.32% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1847080 0.40% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81214151 17.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297416009 64.38% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2127138 0.46% 64.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72011199 15.59% 80.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1542030 0.33% 80.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2092912 0.45% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2282044 0.49% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1471797 0.32% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1847192 0.40% 82.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81214350 17.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462018901 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185501 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.916448 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 22519839 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281050355 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150243576 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7317922 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887209 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 834205750 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 887209 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25305856 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229987183 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14520771 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154096496 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37221386 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 830901673 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 454414 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12058066 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 208457 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22294259 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 992600987 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1804085973 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1109069164 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 462004671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185510 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.916486 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22519882 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281035605 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150243041 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7318726 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 887417 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834212570 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 887417 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25306548 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229981312 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14515163 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154096108 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 37218123 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 830907338 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 454391 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12058587 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 208124 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22290402 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 992604792 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1804097397 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109074070 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 286 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 961883524 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30717461 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460427 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463529 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 38187587 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17040256 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10018392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1266986 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1072258 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825691253 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1151613 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820808364 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 215045 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22448205 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33824600 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 141893 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462018901 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.776569 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.399860 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 961885827 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30718963 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 460377 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 463475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38191150 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17040621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10018939 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1267546 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1072117 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825695768 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1151715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820812543 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 215202 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22450912 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33825927 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 141995 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462004671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.776633 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.399879 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278841075 60.35% 60.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13664119 2.96% 63.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9689206 2.10% 65.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6979280 1.51% 66.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74151695 16.05% 82.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4284933 0.93% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72644295 15.72% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1183606 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 580692 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278825933 60.35% 60.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13663917 2.96% 63.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9689323 2.10% 65.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6980180 1.51% 66.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74150960 16.05% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4285873 0.93% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72643996 15.72% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1183653 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 580836 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462018901 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462004671 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1922566 72.06% 72.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1923038 72.06% 72.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 72.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 72.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.06% # attempts to use FU when none available @@ -439,14 +439,14 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 586085 21.97% 94.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159449 5.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 586062 21.96% 94.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159510 5.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284230 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 792921370 96.60% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149961 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126332 0.02% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284391 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 792925473 96.60% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149981 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126333 0.02% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued @@ -473,96 +473,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18051625 2.20% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9274757 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18051798 2.20% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9274478 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820808364 # Type of FU issued -system.cpu.iq.rate 1.763089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2668100 # FU busy when requested +system.cpu.iq.FU_type_0::total 820812543 # Type of FU issued +system.cpu.iq.rate 1.763151 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2668610 # FU busy when requested system.cpu.iq.fu_busy_rate 0.003251 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2106518335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 849303097 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816525348 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 2106513130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 849310448 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816528938 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 438 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 438 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823192025 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 823196553 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1863548 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1863533 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3085191 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14446 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1597044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3085538 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13954 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1597584 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2095832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68625 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2095829 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68627 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887209 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 206158213 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15645218 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826842866 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 165190 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17040277 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10018392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 682629 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 383889 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14436572 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 477389 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506444 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 983833 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819298071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17680302 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1386078 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 887417 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 206161533 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15636111 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826847483 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 165160 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17040642 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10018939 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 682638 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 383814 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14427518 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13954 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 477334 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506559 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 983893 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819301527 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17680087 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1386795 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26745461 # number of memory reference insts executed -system.cpu.iew.exec_branches 82993620 # Number of branches executed -system.cpu.iew.exec_stores 9065159 # Number of stores executed -system.cpu.iew.exec_rate 1.759845 # Inst execution rate -system.cpu.iew.wb_sent 818824421 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816525502 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638690631 # num instructions producing a value -system.cpu.iew.wb_consumers 1046712832 # num instructions consuming a value -system.cpu.iew.wb_rate 1.753889 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610187 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 22323770 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 26745143 # number of memory reference insts executed +system.cpu.iew.exec_branches 82994335 # Number of branches executed +system.cpu.iew.exec_stores 9065056 # Number of stores executed +system.cpu.iew.exec_rate 1.759905 # Inst execution rate +system.cpu.iew.wb_sent 818828086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816529092 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638693519 # num instructions producing a value +system.cpu.iew.wb_consumers 1046716801 # num instructions consuming a value +system.cpu.iew.wb_rate 1.753950 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610188 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 22326581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1009720 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 855337 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458653605 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.753817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.647498 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 855503 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458638769 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.753878 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.647523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 288196518 62.84% 62.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11088839 2.42% 65.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3639702 0.79% 66.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74471288 16.24% 82.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2429938 0.53% 82.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1624365 0.35% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1000566 0.22% 83.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70851536 15.45% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5350853 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 288181414 62.83% 62.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11088145 2.42% 65.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3640328 0.79% 66.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74471829 16.24% 82.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2429591 0.53% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1624239 0.35% 83.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1000805 0.22% 83.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70851455 15.45% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5350963 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458653605 # Number of insts commited each cycle -system.cpu.commit.committedInsts 406948645 # Number of instructions committed -system.cpu.commit.committedOps 804394656 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458638769 # Number of insts commited each cycle +system.cpu.commit.committedInsts 406949634 # Number of instructions committed +system.cpu.commit.committedOps 804396566 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22376433 # Number of memory references committed -system.cpu.commit.loads 13955085 # Number of loads committed +system.cpu.commit.refs 22376458 # Number of memory references committed +system.cpu.commit.loads 13955103 # Number of loads committed system.cpu.commit.membars 448031 # Number of memory barriers committed -system.cpu.commit.branches 82000673 # Number of branches committed +system.cpu.commit.branches 82000860 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 733377152 # Number of committed integer instructions. +system.cpu.commit.int_insts 733378889 # Number of committed integer instructions. system.cpu.commit.function_calls 1155590 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171815 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 781582591 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::No_OpClass 171811 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 781584496 97.16% 97.19% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 144575 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121813 0.02% 97.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121797 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -589,231 +589,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13952498 1.73% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8421348 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13952516 1.73% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8421355 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 804394656 # Class of committed instruction -system.cpu.commit.bw_lim_events 5350853 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1279942872 # The number of ROB reads -system.cpu.rob.rob_writes 1656820485 # The number of ROB writes -system.cpu.timesIdled 287895 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3532390 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9839075158 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 406948645 # Number of Instructions Simulated -system.cpu.committedOps 804394656 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.144005 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.144005 # CPI: Total CPI of All Threads -system.cpu.ipc 0.874122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.874122 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088092002 # number of integer regfile reads -system.cpu.int_regfile_writes 653524498 # number of integer regfile writes +system.cpu.commit.op_class_0::total 804396566 # Class of committed instruction +system.cpu.commit.bw_lim_events 5350963 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1279932650 # The number of ROB reads +system.cpu.rob.rob_writes 1656830555 # The number of ROB writes +system.cpu.timesIdled 287928 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3532567 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9839087291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 406949634 # Number of Instructions Simulated +system.cpu.committedOps 804396566 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.143968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.143968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.874151 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.874151 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088094227 # number of integer regfile reads +system.cpu.int_regfile_writes 653527011 # number of integer regfile writes system.cpu.fp_regfile_reads 154 # number of floating regfile reads -system.cpu.cc_regfile_reads 414883395 # number of cc regfile reads -system.cpu.cc_regfile_writes 320972082 # number of cc regfile writes -system.cpu.misc_regfile_reads 264296844 # number of misc regfile reads +system.cpu.cc_regfile_reads 414885669 # number of cc regfile reads +system.cpu.cc_regfile_writes 320973068 # number of cc regfile writes +system.cpu.misc_regfile_reads 264298420 # number of misc regfile reads system.cpu.misc_regfile_writes 400155 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1656669 # number of replacements +system.cpu.dcache.tags.replacements 1656768 # number of replacements system.cpu.dcache.tags.tagsinuse 511.992170 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18961321 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1657181 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.441913 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 18961019 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1657280 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.441047 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.992170 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87667052 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87667052 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10819019 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10819019 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8076374 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8076374 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63037 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63037 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18895393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18895393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18958430 # number of overall hits -system.cpu.dcache.overall_hits::total 18958430 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802297 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802297 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 335310 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 335310 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406421 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406421 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2137607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2137607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2544028 # number of overall misses -system.cpu.dcache.overall_misses::total 2544028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30111588500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30111588500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21132348722 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21132348722 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51243937222 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51243937222 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51243937222 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51243937222 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12621316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12621316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411684 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411684 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 469458 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 469458 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21033000 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21033000 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21502458 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21502458 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142798 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.142798 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039862 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039862 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865724 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.865724 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.101631 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.101631 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118313 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118313 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16707.339856 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16707.339856 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63023.317891 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63023.317891 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23972.571769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23972.571769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20142.835386 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20142.835386 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 552183 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87666283 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87666283 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10818711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10818711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8076378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8076378 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63033 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63033 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18895089 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18895089 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18958122 # number of overall hits +system.cpu.dcache.overall_hits::total 18958122 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802383 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802383 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 335313 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 335313 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406423 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406423 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2137696 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2137696 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2544119 # number of overall misses +system.cpu.dcache.overall_misses::total 2544119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30109912500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30109912500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21130469723 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21130469723 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51240382223 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51240382223 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51240382223 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51240382223 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12621094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12621094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8411691 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8411691 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 469456 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 469456 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21032785 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21032785 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21502241 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21502241 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142807 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039863 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039863 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865732 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865732 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101636 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101636 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16705.612792 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16705.612792 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63017.150313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63017.150313 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23969.910700 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23969.910700 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20140.717562 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20140.717562 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 552645 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52307 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 52313 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.556579 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.564200 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1558965 # number of writebacks -system.cpu.dcache.writebacks::total 1558965 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 836189 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 836189 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44847 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44847 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 881036 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 881036 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 881036 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 881036 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 966108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290463 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290463 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402928 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402928 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1256571 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1256571 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1659499 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1659499 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 1559051 # number of writebacks +system.cpu.dcache.writebacks::total 1559051 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 836185 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 836185 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44844 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44844 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 881029 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 881029 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 881029 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 881029 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 966198 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 966198 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290469 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290469 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402930 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402930 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1256667 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1256667 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1659597 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1659597 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13902 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13902 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 587362 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 587362 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14275784000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14275784000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19192933722 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19192933722 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6799517500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6799517500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33468717722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33468717722 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40268235222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40268235222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98146130000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98146130000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778950500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778950500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925080500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925080500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076546 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034531 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034531 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858283 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858283 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059743 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059743 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077177 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14776.592265 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14776.592265 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66077.034672 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66077.034672 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16875.266797 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16875.266797 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26634.959522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26634.959522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24265.296467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24265.296467 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.298853 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.298853 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199895.734427 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199895.734427 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.732301 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.732301 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14276500000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14276500000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19191766223 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19191766223 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6799993500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6799993500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33468266223 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33468266223 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40268259723 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40268259723 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98146110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98146110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2778958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2778958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100925068500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100925068500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076554 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076554 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858291 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858291 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059748 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059748 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077183 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077183 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14775.956895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14775.956895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66071.650410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66071.650410 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16876.364381 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16876.364381 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26632.565527 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26632.565527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24263.878353 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24263.878353 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171147.264848 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171147.264848 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199896.273917 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199896.273917 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171827.711871 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171827.711871 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 70093 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.821930 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 109512 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 70108 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.562047 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.replacements 70166 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.821895 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 109067 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70181 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.554082 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 199860126500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821930 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988871 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988871 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821895 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988868 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988868 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 432670 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 432670 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 109535 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 109535 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 109535 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 109535 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 109535 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 109535 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71200 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 71200 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71200 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 71200 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71200 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 71200 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 922231500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 922231500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 922231500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 922231500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 922231500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 922231500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180735 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 180735 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180735 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 180735 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180735 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 180735 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393947 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393947 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393947 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393947 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393947 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393947 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12952.689607 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12952.689607 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12952.689607 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12952.689607 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12952.689607 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 431964 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 431964 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 109068 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 109068 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 109068 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 109068 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 109068 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 109068 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71276 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71276 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71276 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71276 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71276 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71276 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 917687000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 917687000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 917687000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 917687000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 917687000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 917687000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 180344 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 180344 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 180344 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 180344 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 180344 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 180344 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395222 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395222 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395222 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395222 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395222 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395222 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12875.119255 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12875.119255 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12875.119255 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12875.119255 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12875.119255 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12875.119255 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,133 +822,133 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21274 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21274 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71200 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71200 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71200 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 71200 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71200 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 71200 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 851031500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 851031500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 851031500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 851031500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 851031500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 851031500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.393947 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.393947 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.393947 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.393947 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11952.689607 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11952.689607 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11952.689607 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21382 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21382 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71276 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71276 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71276 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71276 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71276 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71276 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 846411000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 846411000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 846411000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 846411000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 846411000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 846411000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395222 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395222 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395222 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395222 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11875.119255 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11875.119255 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11875.119255 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11875.119255 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 977286 # number of replacements -system.cpu.icache.tags.tagsinuse 509.169987 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7899726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 977798 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.079098 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 977252 # number of replacements +system.cpu.icache.tags.tagsinuse 509.169999 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7899773 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 977764 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.079427 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 150383300500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.169987 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 509.169999 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9921613 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9921613 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7899726 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7899726 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7899726 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7899726 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7899726 # number of overall hits -system.cpu.icache.overall_hits::total 7899726 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1044015 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1044015 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1044015 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1044015 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1044015 # number of overall misses -system.cpu.icache.overall_misses::total 1044015 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15702934482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15702934482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15702934482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15702934482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15702934482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15702934482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8943741 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8943741 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8943741 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8943741 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8943741 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8943741 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116731 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.116731 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.116731 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.116731 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.116731 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.116731 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15040.908878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15040.908878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15040.908878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15040.908878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15040.908878 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15272 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9921559 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9921559 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7899773 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7899773 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7899773 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7899773 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7899773 # number of overall hits +system.cpu.icache.overall_hits::total 7899773 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1043950 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1043950 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1043950 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1043950 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1043950 # number of overall misses +system.cpu.icache.overall_misses::total 1043950 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15700851982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15700851982 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15700851982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15700851982 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15700851982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15700851982 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8943723 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8943723 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8943723 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8943723 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8943723 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8943723 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116724 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116724 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116724 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116724 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116724 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116724 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15039.850550 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15039.850550 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15039.850550 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15039.850550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15039.850550 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15039.850550 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 15298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 183 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 489 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 490 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.231084 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.220408 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 91.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 977286 # number of writebacks -system.cpu.icache.writebacks::total 977286 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66143 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66143 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66143 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 977872 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 977872 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 977872 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 977872 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 977872 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 977872 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13831418488 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13831418488 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13831418488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13831418488 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13831418488 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13831418488 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109336 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109336 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109336 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109336 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109336 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109336 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14144.405902 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14144.405902 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14144.405902 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14144.405902 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14144.405902 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14144.405902 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 977252 # number of writebacks +system.cpu.icache.writebacks::total 977252 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66114 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 66114 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 66114 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 66114 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 66114 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 66114 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 977836 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 977836 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 977836 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 977836 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 977836 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 977836 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13829997488 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13829997488 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13829997488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13829997488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13829997488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13829997488 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109332 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109332 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109332 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109332 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14143.473433 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14143.473433 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14143.473433 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14143.473433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14143.473433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14143.473433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13564 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.033276 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 24089 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13580 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.773859 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.replacements 13555 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.033283 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24087 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 13571 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.774888 # Average number of references to valid blocks. system.cpu.itb_walker_cache.tags.warmup_cycle 5119783334000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.033276 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.033283 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.377080 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.377080 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id @@ -957,48 +957,48 @@ system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 91534 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 91534 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24087 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 24087 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 91500 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 91500 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24085 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24085 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24089 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 24089 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24089 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 24089 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14452 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14452 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14452 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14452 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14452 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14452 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176436500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176436500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176436500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176436500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176436500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176436500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38539 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 38539 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24087 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24087 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24087 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24087 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14442 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 14442 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14442 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 14442 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14442 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 14442 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176053500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176053500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176053500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 176053500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176053500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 176053500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38527 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 38527 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38541 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 38541 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38541 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 38541 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374997 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374997 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374977 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.374977 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374977 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.374977 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12208.448658 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12208.448658 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12208.448658 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12208.448658 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12208.448658 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12208.448658 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38529 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 38529 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38529 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 38529 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374854 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374854 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374835 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.374835 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374835 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.374835 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12190.382219 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12190.382219 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12190.382219 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12190.382219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12190.382219 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12190.382219 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1007,187 +1007,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2638 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2638 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14452 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14452 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14452 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14452 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14452 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14452 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161984500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161984500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161984500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161984500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161984500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161984500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.374997 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.374997 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.374977 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.374977 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.374977 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11208.448658 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11208.448658 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11208.448658 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2646 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2646 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14442 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14442 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14442 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 14442 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14442 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 14442 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 161611500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 161611500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 161611500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 161611500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 161611500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 161611500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.374854 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.374854 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.374835 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.374835 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.374835 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.374835 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11190.382219 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11190.382219 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11190.382219 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11190.382219 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111860 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64806.586551 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4895189 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176141 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.791309 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111866 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64806.585136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4895184 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176146 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.790492 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50665.329006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 16.461622 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 50665.331172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 16.461611 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139358 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3133.882078 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.774487 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3133.879154 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10990.773840 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.773092 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.167706 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.988870 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64280 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 693 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980850 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43507450 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43507450 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1582877 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1582877 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 976140 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 976140 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155489 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155489 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 961542 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 961542 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64982 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12040 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332604 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1409626 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 64982 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12040 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 961542 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1488093 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2526657 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 64982 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12040 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 961542 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1488093 # number of overall hits -system.cpu.l2cache.overall_hits::total 2526657 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1472 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1472 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132824 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132824 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16188 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16188 # number of ReadCleanReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3370 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54078 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.980835 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43505464 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43505464 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1583079 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1583079 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 976106 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 976106 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 322 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 155501 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 155501 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 961509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 961509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 64508 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12006 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332683 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1409197 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64508 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12006 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 961509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1488184 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2526207 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64508 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12006 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 961509 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1488184 # number of overall hits +system.cpu.l2cache.overall_hits::total 2526207 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1468 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1468 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132819 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132819 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16187 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16187 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 64 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35686 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 35755 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35692 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 35761 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 64 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16188 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168510 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16187 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168511 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 184767 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 64 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16188 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168510 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16187 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168511 # number of overall misses system.cpu.l2cache.overall_misses::total 184767 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60587500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 60587500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16987974500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16987974500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2174639000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2174639000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9238000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60416500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 60416500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16987025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16987025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2173573500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2173573500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 9251500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 665000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4801016500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4810919500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9238000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4801171500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4811088000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9251500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2174639000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21788991000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23973533000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9238000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2173573500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 21788196500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23971686500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9251500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2174639000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21788991000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23973533000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1582877 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1582877 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 976140 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 976140 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1798 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1798 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 288313 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 288313 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 977730 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 977730 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 65046 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12045 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368290 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1445381 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 65046 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12045 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 977730 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1656603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2711424 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 65046 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12045 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 977730 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1656603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2711424 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818687 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818687 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.460694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016557 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016557 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000415 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026081 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024737 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000984 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000415 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016557 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101720 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.068144 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000984 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000415 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016557 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101720 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.068144 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41159.986413 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41159.986413 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127898.380564 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127898.380564 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134336.483815 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134336.483815 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144343.750000 # average ReadSharedReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 2173573500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 21788196500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23971686500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1583079 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1583079 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 976106 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 976106 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1790 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1790 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 288320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 288320 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 977696 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 977696 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 64572 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12011 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1368375 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1444958 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64572 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12011 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 977696 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1656695 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2710974 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64572 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12011 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 977696 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1656695 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2710974 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820112 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820112 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460665 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.460665 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016556 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016556 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000991 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.000416 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026083 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024749 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000991 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101715 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068155 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000991 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101715 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068155 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41155.653951 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41155.653951 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127896.046499 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127896.046499 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134278.958423 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134278.958423 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 144554.687500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134535.013731 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134552.356314 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 144343.750000 # average overall miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134516.740446 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134534.492883 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 144554.687500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134336.483815 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129303.845469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 129750.079830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 144343.750000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134278.958423 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 129298.363312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 129740.086163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 144554.687500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134336.483815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129303.845469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 129750.079830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134278.958423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 129298.363312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 129740.086163 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1196,8 +1196,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102429 # number of writebacks -system.cpu.l2cache.writebacks::total 102429 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 102439 # number of writebacks +system.cpu.l2cache.writebacks::total 102439 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 2 # number of ReadSharedReq MSHR hits @@ -1210,25 +1210,25 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 2 system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1472 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1472 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 132824 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16185 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16185 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1468 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1468 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132819 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132819 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16184 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16184 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35684 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35753 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35690 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35759 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 64 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168508 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16184 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168509 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 184762 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 64 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168508 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16184 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 184762 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 573460 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 573460 # number of ReadReq MSHR uncacheable @@ -1236,138 +1236,138 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13902 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13902 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 587362 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 587362 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 105285000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 105285000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15659734500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15659734500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2012557000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2012557000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8598000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 104998500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 104998500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15658835000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15658835000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2011501500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2011501500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 8611500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 615000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4444414500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4453627500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8598000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4444509500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4453736000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8611500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 615000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2012557000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20104149000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22125919000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8598000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2011501500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20103344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22124072500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8611500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 615000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2012557000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20104149000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22125919000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90977838000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90977838000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2619015000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2619015000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93596853000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93596853000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2011501500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20103344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22124072500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 90977820000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 90977820000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2619013000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2619013000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93596833000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93596833000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818687 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818687 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016554 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026079 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024736 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.068142 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000984 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000415 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016554 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101719 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.068142 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71525.135870 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71525.135870 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117898.380564 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117898.380564 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124347.049737 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124347.049737 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820112 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820112 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460665 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460665 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016553 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026082 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024747 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101714 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068153 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016553 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101714 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068153 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71524.863760 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71524.863760 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117896.046499 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117896.046499 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124289.514335 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124289.514335 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124549.223742 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124566.539871 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124530.947044 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124548.673061 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134343.750000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124289.514335 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119301.310316 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119743.629642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 134554.687500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124347.049737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119306.792556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119753.623581 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.225613 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.225613 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.238671 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.238671 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.222926 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.222926 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124289.514335 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119301.310316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119743.629642 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158647.194225 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158647.194225 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188391.094807 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188391.094807 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159351.188875 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159351.188875 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5440647 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2708460 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1238 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5440904 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2708527 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1244 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1244 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3006256 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3006380 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13902 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13902 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1731980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 976140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 117314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 288324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 288324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 977872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1455461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1732191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 976106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117351 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2287 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2287 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288332 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 977836 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1455618 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2931742 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6148479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31127 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 166003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9277351 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125047680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207509531 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 939712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5524480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 339021403 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 218907 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3519115 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019900 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.161788 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2931638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6148755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31077 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9277233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125043328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207521115 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 938048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5501056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 339003547 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 219501 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3519248 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019893 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.161869 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3460821 98.34% 98.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 46556 1.32% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 11738 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3461036 98.35% 98.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 46415 1.32% 99.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 11797 0.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3519115 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5581131973 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3519248 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5581428473 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 669284 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 673784 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1468639319 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1468574841 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3067775714 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3067922715 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21694467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 21677471 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 106870358 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 106983360 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 212021 # Transaction distribution system.iobus.trans_dist::ReadResp 212021 # Transaction distribution @@ -1423,13 +1423,13 @@ system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 3262802 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3986644 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 3986144 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 43000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10458500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10452000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 146500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1443,13 +1443,13 @@ system.iobus.reqLayer8.occupancy 32500 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 300003000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1174000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1174500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 24569000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 24568000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1459,7 +1459,7 @@ system.iobus.reqLayer17.occupancy 10000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 241170809 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 241169809 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1085500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) @@ -1470,12 +1470,12 @@ system.iobus.respLayer1.utilization 0.0 # La system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47574 # number of replacements -system.iocache.tags.tagsinuse 0.140720 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.140717 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 4999394542000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.140720 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.140717 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008795 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.008795 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1491,14 +1491,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 909 system.iocache.demand_misses::total 909 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses system.iocache.overall_misses::total 909 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 150240673 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 150240673 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6073165136 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6073165136 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 150240673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 150240673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 150240673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 150240673 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147582673 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147582673 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6073068136 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6073068136 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 147582673 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 147582673 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 147582673 # number of overall miss cycles +system.iocache.overall_miss_latency::total 147582673 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1515,19 +1515,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 165281.268427 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129990.692123 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129990.692123 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 165281.268427 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165281.268427 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 165281.268427 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1090 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162357.176018 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129988.615925 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129988.615925 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 162357.176018 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162357.176018 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 162357.176018 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 921 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 104 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.480769 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.855769 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1541,14 +1541,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 909 system.iocache.demand_mshr_misses::total 909 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 909 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 909 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104790673 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3737165136 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3737165136 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104790673 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104790673 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104790673 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 102132673 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3737068136 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3737068136 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 102132673 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 102132673 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 102132673 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1557,26 +1557,26 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115281.268427 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79990.692123 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79990.692123 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115281.268427 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115281.268427 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112357.176018 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.615925 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.615925 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 112357.176018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 112357.176018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 112357.176018 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 573460 # Transaction distribution -system.membus.trans_dist::ReadResp 626303 # Transaction distribution +system.membus.trans_dist::ReadResp 626308 # Transaction distribution system.membus.trans_dist::WriteReq 13902 # Transaction distribution system.membus.trans_dist::WriteResp 13902 # Transaction distribution -system.membus.trans_dist::WritebackDirty 149096 # Transaction distribution -system.membus.trans_dist::CleanEvict 9693 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2236 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1746 # Transaction distribution +system.membus.trans_dist::WritebackDirty 149106 # Transaction distribution +system.membus.trans_dist::CleanEvict 9689 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1738 # Transaction distribution system.membus.trans_dist::ReadExReq 132555 # Transaction distribution -system.membus.trans_dist::ReadExResp 132550 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52847 # Transaction distribution +system.membus.trans_dist::ReadExResp 132549 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52852 # Transaction distribution system.membus.trans_dist::MessageReq 1647 # Transaction distribution system.membus.trans_dist::MessageResp 1647 # Transaction distribution system.membus.trans_dist::BadAddressError 4 # Transaction distribution @@ -1586,48 +1586,48 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730488 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484035 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 484041 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 8 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658773 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 141815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1803876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1803882 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460973 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18319744 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20009115 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18320640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20010011 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23030743 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1647 # Total snoops (count) -system.membus.snoop_fanout::samples 982714 # Request fanout histogram +system.membus.pkt_size::total 23031639 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1655 # Total snoops (count) +system.membus.snoop_fanout::samples 982723 # Request fanout histogram system.membus.snoop_fanout::mean 1.001676 # Request fanout histogram system.membus.snoop_fanout::stdev 0.040904 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 981067 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::1 981076 99.83% 99.83% # Request fanout histogram system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 982714 # Request fanout histogram -system.membus.reqLayer0.occupancy 338956500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 982723 # Request fanout histogram +system.membus.reqLayer0.occupancy 338949500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 369067500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 369068500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3986356 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3985856 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1013629759 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1013663510 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 5500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 2339356 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2338856 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2140696281 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2140705292 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85836693 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85841188 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f975cdce3..cc30b102c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.140310 # Number of seconds simulated -sim_ticks 5140310078000 # Number of ticks simulated -final_tick 5140310078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5140310077000 # Number of ticks simulated +final_tick 5140310077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 269101 # Simulator instruction rate (inst/s) -host_op_rate 534933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5691143534 # Simulator tick rate (ticks/s) -host_mem_usage 1043812 # Number of bytes of host memory used -host_seconds 903.21 # Real time elapsed on the host -sim_insts 243055556 # Number of instructions simulated -sim_ops 483158347 # Number of ops (including micro ops) simulated +host_inst_rate 193642 # Simulator instruction rate (inst/s) +host_op_rate 384932 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4095276555 # Simulator tick rate (ticks/s) +host_mem_usage 1038092 # Number of bytes of host memory used +host_seconds 1255.18 # Real time elapsed on the host +sim_insts 243055842 # Number of instructions simulated +sim_ops 483158927 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 444224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 444160 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 355648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3199424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 355968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3200064 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11343552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 444224 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11344576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 444160 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 355648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 957376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9153408 # Number of bytes written to this memory -system.physmem.bytes_written::total 9153408 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 355968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 957632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9154432 # Number of bytes written to this memory +system.physmem.bytes_written::total 9154432 # Number of bytes written to this memory system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6940 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 49991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 50001 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177243 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143022 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143022 # Number of write requests responded to by this memory +system.physmem.num_reads::total 177259 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143038 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143038 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 86420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86407 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 69188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 622418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 69250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 622543 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2206784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 86420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2206983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86407 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 69188 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 186249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1780711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1780711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1780711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 69250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 186298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1780910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1780910 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1780910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 86420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 86407 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 69188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 622418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 69250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 622543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3987495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 86962 # Number of read requests accepted -system.physmem.writeReqs 83127 # Number of write requests accepted -system.physmem.readBursts 86962 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83127 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5558208 # Total number of bytes read from DRAM +system.physmem.bw_total::total 3987893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 86979 # Number of read requests accepted +system.physmem.writeReqs 83143 # Number of write requests accepted +system.physmem.readBursts 86979 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5559296 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 5320128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5565568 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5320128 # Total written bytes from the system interface side +system.physmem.bytesWritten 5321152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5566656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5321152 # Total written bytes from the system interface side system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 33935 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5197 # Per bank write bursts -system.physmem.perBankRdBursts::1 4660 # Per bank write bursts -system.physmem.perBankRdBursts::2 5410 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 33940 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5203 # Per bank write bursts +system.physmem.perBankRdBursts::1 4657 # Per bank write bursts +system.physmem.perBankRdBursts::2 5413 # Per bank write bursts system.physmem.perBankRdBursts::3 5303 # Per bank write bursts -system.physmem.perBankRdBursts::4 5131 # Per bank write bursts -system.physmem.perBankRdBursts::5 4781 # Per bank write bursts +system.physmem.perBankRdBursts::4 5134 # Per bank write bursts +system.physmem.perBankRdBursts::5 4786 # Per bank write bursts system.physmem.perBankRdBursts::6 5593 # Per bank write bursts -system.physmem.perBankRdBursts::7 5451 # Per bank write bursts -system.physmem.perBankRdBursts::8 5257 # Per bank write bursts -system.physmem.perBankRdBursts::9 4895 # Per bank write bursts -system.physmem.perBankRdBursts::10 5205 # Per bank write bursts -system.physmem.perBankRdBursts::11 5208 # Per bank write bursts -system.physmem.perBankRdBursts::12 5485 # Per bank write bursts +system.physmem.perBankRdBursts::7 5448 # Per bank write bursts +system.physmem.perBankRdBursts::8 5260 # Per bank write bursts +system.physmem.perBankRdBursts::9 4897 # Per bank write bursts +system.physmem.perBankRdBursts::10 5208 # Per bank write bursts +system.physmem.perBankRdBursts::11 5207 # Per bank write bursts +system.physmem.perBankRdBursts::12 5484 # Per bank write bursts system.physmem.perBankRdBursts::13 6574 # Per bank write bursts system.physmem.perBankRdBursts::14 6603 # Per bank write bursts system.physmem.perBankRdBursts::15 6094 # Per bank write bursts -system.physmem.perBankWrBursts::0 5588 # Per bank write bursts +system.physmem.perBankWrBursts::0 5594 # Per bank write bursts system.physmem.perBankWrBursts::1 5124 # Per bank write bursts -system.physmem.perBankWrBursts::2 5267 # Per bank write bursts -system.physmem.perBankWrBursts::3 4836 # Per bank write bursts -system.physmem.perBankWrBursts::4 5431 # Per bank write bursts -system.physmem.perBankWrBursts::5 5206 # Per bank write bursts -system.physmem.perBankWrBursts::6 5103 # Per bank write bursts -system.physmem.perBankWrBursts::7 5105 # Per bank write bursts -system.physmem.perBankWrBursts::8 5093 # Per bank write bursts -system.physmem.perBankWrBursts::9 5184 # Per bank write bursts -system.physmem.perBankWrBursts::10 5317 # Per bank write bursts -system.physmem.perBankWrBursts::11 5091 # Per bank write bursts -system.physmem.perBankWrBursts::12 4613 # Per bank write bursts +system.physmem.perBankWrBursts::2 5270 # Per bank write bursts +system.physmem.perBankWrBursts::3 4838 # Per bank write bursts +system.physmem.perBankWrBursts::4 5433 # Per bank write bursts +system.physmem.perBankWrBursts::5 5211 # Per bank write bursts +system.physmem.perBankWrBursts::6 5102 # Per bank write bursts +system.physmem.perBankWrBursts::7 5101 # Per bank write bursts +system.physmem.perBankWrBursts::8 5096 # Per bank write bursts +system.physmem.perBankWrBursts::9 5186 # Per bank write bursts +system.physmem.perBankWrBursts::10 5320 # Per bank write bursts +system.physmem.perBankWrBursts::11 5088 # Per bank write bursts +system.physmem.perBankWrBursts::12 4612 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5354 # Per bank write bursts +system.physmem.perBankWrBursts::14 5353 # Per bank write bursts system.physmem.perBankWrBursts::15 5452 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 5136428746000 # Total gap between requests +system.physmem.totGap 5136428721000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 86962 # Read request sizes (log2) +system.physmem.readPktSize::6 86979 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83127 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 81204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83143 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see @@ -176,98 +176,98 @@ system.physmem.wrQLenPdf::11 53 # Wh system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4990 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39704 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.985896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.719261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 301.548634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16089 40.52% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9815 24.72% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4115 10.36% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2259 5.69% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1546 3.89% 85.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1077 2.71% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 717 1.81% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 581 1.46% 91.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3505 8.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39704 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4014 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.636024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 232.585773 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4011 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 39730 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 273.859753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.661250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.445638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16103 40.53% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9824 24.73% 65.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4113 10.35% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2266 5.70% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1547 3.89% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1072 2.70% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 721 1.81% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 578 1.45% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3506 8.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39730 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.613337 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.441160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4016 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4014 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4014 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.709268 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.149216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.865339 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.687484 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.141176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.818199 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3286 81.86% 83.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 102 2.54% 86.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.77% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 110 2.74% 89.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 16 0.40% 90.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 107 2.67% 92.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 56 1.40% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.07% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.30% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.50% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.10% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 148 3.69% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3291 81.89% 83.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 104 2.59% 86.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.80% 87.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 108 2.69% 89.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 15 0.37% 90.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 105 2.61% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 59 1.47% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.10% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.35% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.50% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.05% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.10% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 144 3.58% 98.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads @@ -280,90 +280,90 @@ system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Wr system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4014 # Writes before turning the bus around for reads -system.physmem.totQLat 1058164225 # Total ticks spent queuing -system.physmem.totMemAccLat 2686545475 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 434235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12184.23 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads +system.physmem.totQLat 1059562475 # Total ticks spent queuing +system.physmem.totMemAccLat 2688262475 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 434320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12197.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30934.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30947.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.03 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.03 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing -system.physmem.readRowHits 68775 # Number of row buffer hits during reads -system.physmem.writeRowHits 61495 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.19 # Row buffer hit rate for reads +system.physmem.readRowHits 68770 # Number of row buffer hits during reads +system.physmem.writeRowHits 61507 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes -system.physmem.avgGap 30198476.95 # Average gap between requests -system.physmem.pageHitRate 76.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 145461960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79191750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 323902800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 269956800 # Energy for write commands per rank (pJ) +system.physmem.avgGap 30192618.95 # Average gap between requests +system.physmem.pageHitRate 76.63 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 145673640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 79307250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 323988600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 270041040 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96312598470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2240118682500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2587633207560 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.890236 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3686035921978 # Time in different power states +system.physmem_0.actBackEnergy 96324881400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2240107908000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2587635213210 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.890753 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3686018034728 # Time in different power states system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19846503022 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19864390272 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 154700280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 84191250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 353503800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 268706160 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 154685160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 84187125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 353550600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 268725600 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96598721655 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2233305647250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581148883675 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.102542 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3685636098978 # Time in different power states +system.physmem_1.actBackEnergy 96580278450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233317414750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2581142254965 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.102097 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3685663172228 # Time in different power states system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20213469772 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20186348022 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1072285216 # number of cpu cycles simulated +system.cpu0.numCycles 1072285093 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 71949475 # Number of instructions committed +system.cpu0.committedInsts 71949472 # Number of instructions committed system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134558001 # Number of integer alu accesses +system.cpu0.num_int_alu_accesses 134558000 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 963710 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134558001 # number of integer instructions +system.cpu0.num_int_insts 134558000 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246915369 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115616478 # number of times the integer registers were written +system.cpu0.num_int_register_reads 246915381 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115616486 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55920141 # number of times the CC registers were written +system.cpu0.num_cc_register_writes 55920138 # number of times the CC registers were written system.cpu0.num_mem_refs 13826864 # number of memory refs system.cpu0.num_load_insts 10217566 # Number of load instructions system.cpu0.num_store_insts 3609298 # Number of store instructions -system.cpu0.num_idle_cycles 1017808473.109560 # Number of idle cycles -system.cpu0.num_busy_cycles 54476742.890440 # Number of busy cycles +system.cpu0.num_idle_cycles 1017808343.518800 # Number of idle cycles +system.cpu0.num_busy_cycles 54476749.481200 # Number of busy cycles system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles system.cpu0.Branches 15573120 # Number of branches fetched -system.cpu0.op_class::No_OpClass 93860 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132602493 90.43% 90.50% # Class of executed instruction +system.cpu0.op_class::No_OpClass 93861 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132602488 90.43% 90.50% # Class of executed instruction system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 49730 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 49734 0.03% 90.57% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction @@ -395,17 +395,17 @@ system.cpu0.op_class::MemWrite 3609298 2.46% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 146630109 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1637599 # number of replacements +system.cpu0.dcache.tags.replacements 1637608 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999082 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19598772 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1638111 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.964252 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 19599059 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638120 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.964361 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195837 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604771 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198475 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195835 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604713 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198534 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359757 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413291 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413290 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226950 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999998 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -413,149 +413,149 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 241 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88194499 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88194499 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4977444 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2398985 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4079357 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11455786 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3466929 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1632241 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2982365 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8081535 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 88196204 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88196204 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4977443 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2399002 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4079601 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11456046 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3466928 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1632244 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2982379 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8081551 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 21705 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9720 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28159 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59584 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8444373 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4031226 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7061722 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19537321 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8466078 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4040946 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7089881 # number of overall hits -system.cpu0.dcache.overall_hits::total 19596905 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 370513 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 153426 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 785141 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1309080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 138237 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28160 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 59585 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8444371 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4031246 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7061980 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19537597 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8466076 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4040966 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7090140 # number of overall hits +system.cpu0.dcache.overall_hits::total 19597182 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 370514 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 153427 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 785283 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1309224 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 138238 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 55177 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu2.data 133227 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 326641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 326642 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 157440 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58723 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190305 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406468 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 508750 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 208603 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 918368 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1635721 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 666190 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 267326 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1108673 # number of overall misses -system.cpu0.dcache.overall_misses::total 2042189 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2248360000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12710748500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14959108500 # number of ReadReq miss cycles +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190307 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406470 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 508752 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 208604 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 918510 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1635866 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 666192 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 267327 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1108817 # number of overall misses +system.cpu0.dcache.overall_misses::total 2042336 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2248261000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12713989500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14962250500 # number of ReadReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 3673730495 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6566018901 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10239749396 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5922090495 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 19276767401 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25198857896 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5922090495 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 19276767401 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25198857896 # number of overall miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6566436401 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10240166896 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5921991495 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 19280425901 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25202417396 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5921991495 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 19280425901 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25202417396 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 5347957 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2552411 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4864498 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12764866 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2552429 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4864884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12765270 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3605166 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1687418 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3115592 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8408176 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1687421 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3115606 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8408193 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 179145 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 68443 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218464 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466052 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218467 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466055 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 8953123 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4239829 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7980090 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21173042 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4239850 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7980490 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21173463 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 9132268 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4308272 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8198554 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21639094 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4308293 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8198957 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21639518 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069281 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060110 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161402 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.102553 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.102561 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038344 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.032699 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042761 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.038848 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.878841 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.857984 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871105 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872152 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871102 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872150 # miss rate for SoftPFReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056824 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049201 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115082 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.077255 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115094 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.077260 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072949 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062049 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135228 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094375 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14654.361060 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16189.128450 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11427.191997 # average ReadReq miss latency +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.094380 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14653.620288 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16190.328200 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11428.335029 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66580.830690 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49284.446103 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31348.634727 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28389.287283 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.242910 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15405.352072 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22153.065901 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17387.243489 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12339.140939 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 206703 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49287.579852 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31349.816913 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28388.676607 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.980938 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15406.162483 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22152.612699 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17388.284903 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12339.995670 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 206528 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22011 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21989 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.390895 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.392333 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1548077 # number of writebacks -system.cpu0.dcache.writebacks::total 1548077 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1548069 # number of writebacks +system.cpu0.dcache.writebacks::total 1548069 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 363716 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 363786 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 363845 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363915 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1660 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33557 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 35217 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33563 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35223 # number of WriteReq MSHR hits system.cpu0.dcache.demand_mshr_hits::cpu1.data 1730 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 397273 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 399003 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 397408 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 399138 # number of demand (read+write) MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu1.data 1730 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 397273 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 399003 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 153356 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 421425 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 574781 # number of ReadReq MSHR misses +system.cpu0.dcache.overall_mshr_hits::cpu2.data 397408 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 399138 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 153357 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 421438 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 574795 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 53517 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99670 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 153187 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99664 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 153181 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58722 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186896 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 245618 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 206873 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 521095 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 727968 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 265595 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 707991 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 973586 # number of overall MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186898 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 245620 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 206874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 521102 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 727976 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 265596 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 708000 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 973596 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable @@ -565,82 +565,82 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6370 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2092039500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 6051222000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8143261500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2091939500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 6052493500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8144433000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3446784995 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5707170401 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9153955396 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1012070500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960619500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3972690000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5538824495 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11758392401 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17297216896 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6550894995 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14719011901 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21269906896 # number of overall MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5707366401 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9154151396 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1012257500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3973027000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5538724495 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11759859901 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17298584396 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6550981995 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14720629401 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21271611396 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30675451000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32998765500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63674216500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32998770000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63674221000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 673827500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612020000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285847500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612008500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285836000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31349278500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610785500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960064000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610778500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960057000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060083 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086633 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086629 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045028 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031715 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018219 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018218 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857969 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855500 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527018 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855498 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527019 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048793 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065299 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065297 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.034382 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061648 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086356 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086352 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.044992 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13641.719268 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14358.953550 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14167.589917 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13640.978240 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14361.527674 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14169.282962 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57260.664202 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59756.737817 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17234.946017 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15840.999807 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.262473 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26774.032837 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22564.776866 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23760.957756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24664.978614 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20789.829109 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21846.972837 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57266.078032 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59760.357982 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17238.130513 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15841.632869 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16175.502809 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26773.420029 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22567.289899 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23762.575134 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24665.213313 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20791.849436 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21848.499168 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.868883 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.203532 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.892136 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.215699 # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212802.503477 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201859.890110 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212798.504868 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201858.084772 # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.088453 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172666.018107 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.052811 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172665.999500 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 862079 # number of replacements +system.cpu0.icache.tags.replacements 862096 # number of replacements system.cpu0.icache.tags.tagsinuse 510.743965 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129387157 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 862591 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 149.998269 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 129388053 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 862608 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 149.996352 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 149036221500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.474513 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 126.887139 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.382314 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.474426 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 126.886783 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.382757 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286083 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.247826 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.463637 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.463638 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id @@ -648,156 +648,156 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 system.cpu0.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131136403 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131136403 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87656734 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 38708215 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3022208 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129387157 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87656734 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 38708215 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3022208 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129387157 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87656734 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 38708215 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3022208 # number of overall hits -system.cpu0.icache.overall_hits::total 129387157 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 322605 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 163640 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 400399 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 886644 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 322605 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 163640 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 400399 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 886644 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 322605 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 163640 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 400399 # number of overall misses -system.cpu0.icache.overall_misses::total 886644 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424218000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5939623464 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8363841464 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2424218000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5939623464 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8363841464 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2424218000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5939623464 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8363841464 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87979339 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 38871855 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3422607 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130273801 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87979339 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 38871855 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3422607 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130273801 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87979339 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 38871855 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3422607 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130273801 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 131137351 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 131137351 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 87656735 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38708289 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3023029 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129388053 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87656735 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38708289 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3023029 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129388053 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87656735 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38708289 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3023029 # number of overall hits +system.cpu0.icache.overall_hits::total 129388053 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 322601 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 163645 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 400432 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 886678 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 322601 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 163645 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 400432 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 886678 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 322601 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 163645 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 400432 # number of overall misses +system.cpu0.icache.overall_misses::total 886678 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424283000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943999964 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8368282964 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2424283000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5943999964 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8368282964 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2424283000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5943999964 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8368282964 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87979336 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38871934 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3423461 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130274731 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87979336 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38871934 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3423461 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130274731 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87979336 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38871934 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3423461 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130274731 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003667 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004210 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116987 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116967 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.006806 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003667 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004210 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116987 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116967 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.006806 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003667 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004210 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116987 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116967 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.006806 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.336348 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14834.261484 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9433.145055 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.336348 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14834.261484 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9433.145055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.336348 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14834.261484 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9433.145055 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 13267 # number of cycles access was blocked +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.280913 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14843.968424 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9437.792484 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.280913 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14843.968424 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9437.792484 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.280913 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14843.968424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9437.792484 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 12787 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 575 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 569 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.073043 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.472759 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 862079 # number of writebacks -system.cpu0.icache.writebacks::total 862079 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24042 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 24042 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 24042 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 24042 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 24042 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 24042 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163640 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376357 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539997 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 163640 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 376357 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539997 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 163640 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 376357 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539997 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2260578000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5251926966 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7512504966 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2260578000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5251926966 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7512504966 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260578000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5251926966 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7512504966 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 862096 # number of writebacks +system.cpu0.icache.writebacks::total 862096 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24058 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24058 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24058 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24058 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24058 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24058 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163645 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376374 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 540019 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 163645 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376374 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 540019 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 163645 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376374 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 540019 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2260638000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5253786466 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7514424466 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2260638000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5253786466 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7514424466 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260638000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5253786466 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7514424466 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004145 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.004145 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109962 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.004145 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13912.123523 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.336348 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13954.641380 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13912.123523 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13915.111257 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13915.111257 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13915.111257 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606017772 # number of cpu cycles simulated +system.cpu1.numCycles 2606017773 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 35434797 # Number of instructions committed -system.cpu1.committedOps 68967057 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 63950611 # Number of integer alu accesses +system.cpu1.committedInsts 35434857 # Number of instructions committed +system.cpu1.committedOps 68967174 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63950727 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 471158 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6540301 # number of instructions that are conditional controls -system.cpu1.num_int_insts 63950611 # number of integer instructions +system.cpu1.num_func_calls 471160 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6540311 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63950727 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 118144126 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55187106 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118144335 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55187205 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36132535 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26987071 # number of times the CC registers were written -system.cpu1.num_mem_refs 4484181 # number of memory refs -system.cpu1.num_load_insts 2795215 # Number of load instructions -system.cpu1.num_store_insts 1688966 # Number of store instructions -system.cpu1.num_idle_cycles 2475079667.780020 # Number of idle cycles -system.cpu1.num_busy_cycles 130938104.219980 # Number of busy cycles +system.cpu1.num_cc_register_reads 36132607 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26987111 # number of times the CC registers were written +system.cpu1.num_mem_refs 4484202 # number of memory refs +system.cpu1.num_load_insts 2795233 # Number of load instructions +system.cpu1.num_store_insts 1688969 # Number of store instructions +system.cpu1.num_idle_cycles 2475079638.158952 # Number of idle cycles +system.cpu1.num_busy_cycles 130938134.841048 # Number of busy cycles system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles -system.cpu1.Branches 7181908 # Number of branches fetched +system.cpu1.Branches 7181922 # Number of branches fetched system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64398957 93.38% 93.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 64399053 93.38% 93.42% # Class of executed instruction system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction @@ -826,149 +826,149 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction -system.cpu1.op_class::MemRead 2793855 4.05% 97.55% # Class of executed instruction -system.cpu1.op_class::MemWrite 1688966 2.45% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 2793873 4.05% 97.55% # Class of executed instruction +system.cpu1.op_class::MemWrite 1688969 2.45% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68967226 # Class of executed instruction -system.cpu2.branchPred.lookups 28923329 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28923329 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 299282 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26177543 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25594622 # Number of BTB hits +system.cpu1.op_class::total 68967343 # Class of executed instruction +system.cpu2.branchPred.lookups 28923833 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28923833 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 299320 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26177104 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25594852 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.773202 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 576797 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63162 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157005453 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.775720 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 576883 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63148 # Number of incorrect RAS predictions. +system.cpu2.numCycles 157005173 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10540975 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142872413 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28923329 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26171419 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144748563 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 631577 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 103277 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 10541640 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142873863 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28923833 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26171735 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 144747848 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 631807 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102981 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 10810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 68344 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingTrapStallCycles 69710 # Number of stall cycles due to pending traps system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1893 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3422619 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 155063 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2960 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 155796605 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.805087 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.007326 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.IcacheWaitRetryStallCycles 1766 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3423471 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 155018 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2920 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 155797854 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.805083 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.007319 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100986274 64.82% 64.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 876971 0.56% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23450168 15.05% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 581136 0.37% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 798057 0.51% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 839354 0.54% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 536255 0.34% 82.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 727896 0.47% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27000494 17.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 100986987 64.82% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 876917 0.56% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23450339 15.05% 80.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 581596 0.37% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 798015 0.51% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 839359 0.54% 81.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 536249 0.34% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 727748 0.47% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27000644 17.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155796605 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184219 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.909984 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9166270 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95860787 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22254534 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3994693 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 316440 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278480395 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 316440 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10781716 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77380942 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5123914 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 24366684 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13623085 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277321096 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 194260 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5340054 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 70865 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 6669514 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331396172 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605049332 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371619608 # Number of integer rename lookups +system.cpu2.fetch.rateDist::total 155797854 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184222 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909995 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9166837 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95859954 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22256485 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3994112 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 316555 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278482972 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 316555 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10781931 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77376747 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5125883 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24368379 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13624506 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277324695 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 194123 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5339465 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 70652 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6671965 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331399724 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605057293 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371622887 # Number of integer rename lookups system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320040545 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11355627 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 162880 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 164114 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19801512 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6563978 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3714528 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 447098 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 397095 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275506715 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 407720 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273559358 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 95175 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8352705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12694060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 62726 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155796605 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.755875 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.385543 # Number of insts issued each cycle +system.cpu2.rename.CommittedMaps 320041085 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11358639 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162877 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 164126 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19798687 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6564509 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3714734 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 445796 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 396085 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275510749 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 407738 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273563069 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 95252 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8356294 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12697185 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62746 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155797854 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.755885 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.385565 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93882329 60.26% 60.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5118192 3.29% 63.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3721128 2.39% 65.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3254343 2.09% 68.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23198440 14.89% 82.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2207021 1.42% 84.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23723391 15.23% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 467418 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 224343 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 93882941 60.26% 60.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5118927 3.29% 63.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3721264 2.39% 65.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3253797 2.09% 68.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23197295 14.89% 82.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2207034 1.42% 84.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23724652 15.23% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 467591 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 224353 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155796605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155797854 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1207560 81.79% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 207213 14.03% 95.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61669 4.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1207723 81.78% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.78% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 207267 14.03% 95.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 61876 4.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 77609 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263069409 96.17% 96.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56423 0.02% 96.21% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50250 0.02% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 77671 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263072310 96.17% 96.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56421 0.02% 96.21% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50248 0.02% 96.23% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued @@ -995,96 +995,96 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6863260 2.51% 98.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3442333 1.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6863613 2.51% 98.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3442732 1.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273559358 # Type of FU issued -system.cpu2.iq.rate 1.742356 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1476442 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005397 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 704486629 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284271419 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272061524 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 273563069 # Type of FU issued +system.cpu2.iq.rate 1.742383 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1476866 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005399 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 704495801 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284279079 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272064636 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 274958042 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 274962115 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 723498 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 723478 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1134318 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5680 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5091 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 595155 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1134849 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5659 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5111 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 595348 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 712054 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23601 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 712058 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23525 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 316440 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69933639 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4486006 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 275914435 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 35023 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6563978 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3714528 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 243237 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 162474 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 4012628 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5091 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 167077 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 180895 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347972 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273011944 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6727791 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 497508 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 316555 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69932049 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4483827 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275918487 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 35063 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6564509 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3714734 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 243249 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162438 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4010481 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5111 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 167096 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 181001 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 348097 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273015158 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6728091 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 497866 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10089541 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27708179 # Number of branches executed -system.cpu2.iew.exec_stores 3361750 # Number of stores executed -system.cpu2.iew.exec_rate 1.738869 # Inst execution rate -system.cpu2.iew.wb_sent 272840114 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272061642 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212265363 # num instructions producing a value -system.cpu2.iew.wb_consumers 348191102 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.732817 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609623 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 8350016 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 344994 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 302940 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 154548999 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.731242 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.636335 # Number of insts commited each cycle +system.cpu2.iew.exec_refs 10090158 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27708578 # Number of branches executed +system.cpu2.iew.exec_stores 3362067 # Number of stores executed +system.cpu2.iew.exec_rate 1.738893 # Inst execution rate +system.cpu2.iew.wb_sent 272843265 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272064754 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212267822 # num instructions producing a value +system.cpu2.iew.wb_consumers 348193993 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.732839 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609625 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 8353767 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 344992 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 303032 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 154549869 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.731235 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.636337 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 97452573 63.06% 63.06% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4255618 2.75% 65.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1276058 0.83% 66.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24388972 15.78% 82.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 952831 0.62% 83.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 707614 0.46% 83.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 433779 0.28% 83.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23017420 14.89% 98.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2064134 1.34% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 97453895 63.06% 63.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4255487 2.75% 65.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1275451 0.83% 66.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24388605 15.78% 82.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 953115 0.62% 83.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 708142 0.46% 83.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 433200 0.28% 83.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23018173 14.89% 98.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2063801 1.34% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 154548999 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135671284 # Number of instructions committed -system.cpu2.commit.committedOps 267561730 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 154549869 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135671513 # Number of instructions committed +system.cpu2.commit.committedOps 267562193 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8549033 # Number of memory references committed +system.cpu2.commit.refs 8549046 # Number of memory references committed system.cpu2.commit.loads 5429660 # Number of loads committed system.cpu2.commit.membars 149565 # Number of memory barriers committed -system.cpu2.commit.branches 27339879 # Number of branches committed +system.cpu2.commit.branches 27339925 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244517945 # Number of committed integer instructions. -system.cpu2.commit.function_calls 438137 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 46306 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 258863559 96.75% 96.77% # Class of committed instruction +system.cpu2.commit.int_insts 244518367 # Number of committed integer instructions. +system.cpu2.commit.function_calls 438140 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46308 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258864003 96.75% 96.77% # Class of committed instruction system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48345 0.02% 96.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48349 0.02% 96.80% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction @@ -1112,30 +1112,30 @@ system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3119373 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3119386 1.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267561730 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2064134 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 428366748 # The number of ROB reads -system.cpu2.rob.rob_writes 553077080 # The number of ROB writes -system.cpu2.timesIdled 112413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1208848 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4910585835 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135671284 # Number of Instructions Simulated -system.cpu2.committedOps 267561730 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.157249 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.157249 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.864118 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.864118 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 363754203 # number of integer regfile reads -system.cpu2.int_regfile_writes 218036965 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 267562193 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2063801 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 428372162 # The number of ROB reads +system.cpu2.rob.rob_writes 553085882 # The number of ROB writes +system.cpu2.timesIdled 112358 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1207319 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4910585893 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135671513 # Number of Instructions Simulated +system.cpu2.committedOps 267562193 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.157245 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.157245 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.864121 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.864121 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363757841 # number of integer regfile reads +system.cpu2.int_regfile_writes 218039219 # number of integer regfile writes system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138800226 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106739606 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88774953 # number of misc regfile reads -system.cpu2.misc_regfile_writes 143862 # number of misc regfile writes +system.cpu2.cc_regfile_reads 138801079 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106740366 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88776769 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143860 # number of misc regfile writes system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution @@ -1190,13 +1190,13 @@ system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2378920 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2378420 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 5419500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5416500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1224,7 +1224,7 @@ system.iobus.reqLayer17.occupancy 10500 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 144387981 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 144387481 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) @@ -1256,14 +1256,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 914 system.iocache.demand_misses::total 914 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses system.iocache.overall_misses::total 914 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880276 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126880276 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631346705 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 3631346705 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126880276 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126880276 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126880276 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126880276 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880776 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 126880776 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631478705 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3631478705 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 126880776 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 126880776 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 126880776 # number of overall miss cycles +system.iocache.overall_miss_latency::total 126880776 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1280,19 +1280,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138818.682713 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77725.742830 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 77725.742830 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138818.682713 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138818.682713 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138818.682713 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 745 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138819.229759 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77728.568172 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 77728.568172 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138819.229759 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138819.229759 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 769 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 69 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 71 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.797101 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.830986 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1306,14 +1306,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 89080276 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234546705 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2234546705 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 89080276 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080276 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 89080276 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 89080776 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234678705 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2234678705 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 89080776 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 89080776 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.827133 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.597945 # mshr miss rate for WriteLineReq accesses @@ -1322,31 +1322,31 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827133 system.iocache.demand_mshr_miss_rate::total 0.827133 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.827133 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.052910 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79988.069337 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79988.069337 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117831.052910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.052910 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117831.052910 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.714286 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79992.794423 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79992.794423 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104604 # number of replacements -system.l2c.tags.tagsinuse 64807.192442 # Cycle average of tags in use -system.l2c.tags.total_refs 4639119 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168682 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.502158 # Average number of references to valid blocks. +system.l2c.tags.replacements 104623 # number of replacements +system.l2c.tags.tagsinuse 64807.193930 # Cycle average of tags in use +system.l2c.tags.total_refs 4639141 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168699 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.499517 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51005.596123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 51005.580247 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1646.370611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4933.032602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 515.170721 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1886.198863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.247587 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 884.114832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3927.326006 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.778284 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 1646.367272 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4933.030076 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 515.170725 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1886.196797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.248761 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 884.127622 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3927.337333 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.778283 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.025122 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.075272 # Average percentage of cache occupancy @@ -1356,251 +1356,251 @@ system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 system.l2c.tags.occ_percent::cpu2.inst 0.013491 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.059926 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.988879 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64078 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 64076 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6913 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.977753 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 41426818 # Number of tag accesses -system.l2c.tags.data_accesses 41426818 # Number of data accesses +system.l2c.tags.age_task_id_blocks_1024::3 6926 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54004 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977722 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 41427151 # Number of tag accesses +system.l2c.tags.data_accesses 41427151 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 20684 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 10937 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 10806 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 5737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 57360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 12726 # number of ReadReq hits -system.l2c.ReadReq_hits::total 118250 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 57444 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 12625 # number of ReadReq hits +system.l2c.ReadReq_hits::total 118233 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.WritebackDirty_hits::writebacks 1548077 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1548077 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 861736 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 861736 # number of WritebackClean hits +system.l2c.WritebackDirty_hits::writebacks 1548069 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1548069 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 861756 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 861756 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 113 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 274 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 115 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 276 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 69082 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 29187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 61550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 159819 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 315651 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 161179 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 370786 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 847616 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 512536 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 207467 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 595550 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 1315553 # number of ReadSharedReq hits +system.l2c.ReadExReq_hits::cpu2.data 61537 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159806 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 315648 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 161184 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 370798 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 847630 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 512537 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 207468 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 595557 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 1315562 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 20684 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 10939 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 315651 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 581618 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 315648 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 581619 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 10806 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 5737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 161179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 236654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 57360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 12726 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 370786 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 657100 # number of demand (read+write) hits -system.l2c.demand_hits::total 2441240 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 161184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 236655 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 57444 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 12625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 370798 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 657094 # number of demand (read+write) hits +system.l2c.demand_hits::total 2441233 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 20684 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 10939 # number of overall hits -system.l2c.overall_hits::cpu0.inst 315651 # number of overall hits -system.l2c.overall_hits::cpu0.data 581618 # number of overall hits +system.l2c.overall_hits::cpu0.inst 315648 # number of overall hits +system.l2c.overall_hits::cpu0.data 581619 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 10806 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 5737 # number of overall hits -system.l2c.overall_hits::cpu1.inst 161179 # number of overall hits -system.l2c.overall_hits::cpu1.data 236654 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 57360 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 12726 # number of overall hits -system.l2c.overall_hits::cpu2.inst 370786 # number of overall hits -system.l2c.overall_hits::cpu2.data 657100 # number of overall hits -system.l2c.overall_hits::total 2441240 # number of overall hits +system.l2c.overall_hits::cpu1.inst 161184 # number of overall hits +system.l2c.overall_hits::cpu1.data 236655 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 57444 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 12625 # number of overall hits +system.l2c.overall_hits::cpu2.inst 370798 # number of overall hits +system.l2c.overall_hits::cpu2.data 657094 # number of overall hits +system.l2c.overall_hits::total 2441233 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 706 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses +system.l2c.ReadReq_misses::total 38 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 707 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 151 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 525 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1382 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1383 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 68319 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 24150 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 37534 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130003 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 6941 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::cpu2.data 37538 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130007 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 6940 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 2461 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 5558 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 14960 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 5563 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 14964 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 15417 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 4611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 12720 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 32748 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2.data 12729 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 32757 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6941 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6940 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 83736 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 2461 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 28761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5558 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 50254 # number of demand (read+write) misses -system.l2c.demand_misses::total 177747 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 33 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 50267 # number of demand (read+write) misses +system.l2c.demand_misses::total 177766 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6941 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6940 # number of overall misses system.l2c.overall_misses::cpu0.data 83736 # number of overall misses system.l2c.overall_misses::cpu1.inst 2461 # number of overall misses system.l2c.overall_misses::cpu1.data 28761 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5558 # number of overall misses -system.l2c.overall_misses::cpu2.data 50254 # number of overall misses -system.l2c.overall_misses::total 177747 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 4350500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 4350500 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu2.dtb.walker 33 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5563 # number of overall misses +system.l2c.overall_misses::cpu2.data 50267 # number of overall misses +system.l2c.overall_misses::total 177766 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 4629000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 4629000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 6534500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 19951500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 26486000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 20109000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 26643500 # number of UpgradeReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 3047020000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 4863369000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7910389000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 4863678000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7910698000 # number of ReadExReq miss cycles system.l2c.ReadCleanReq_miss_latency::cpu1.inst 320798500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 757296000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1078094500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 606081000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 1751621500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 2357702500 # number of ReadSharedReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu2.inst 758990000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1079788500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 606156000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 1752917000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 2359073000 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu1.inst 320798500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3653101000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 4350500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 757296000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 6614990500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11350536500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3653176000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 4629000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 758990000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 6616595000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11354188500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.inst 320798500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3653101000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 4350500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 757296000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 6614990500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11350536500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3653176000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 4629000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 758990000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 6616595000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11354188500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 20684 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 10942 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 10806 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 5737 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 57391 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 12726 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 118286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 57477 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 12625 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 118271 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 1548077 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1548077 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 861736 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 861736 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 836 # number of UpgradeReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 1548069 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1548069 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 861756 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 861756 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 837 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 182 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 638 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1656 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 640 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 137401 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 53337 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 99084 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 289822 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 322592 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 163640 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 376344 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 862576 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 527953 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 212078 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 608270 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1348301 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 99075 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 289813 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 322588 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 163645 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu2.inst 376361 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 862594 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 527954 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 212079 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2.data 608286 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1348319 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 20684 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 10944 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 322592 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 665354 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 322588 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 665355 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 10806 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 5737 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 163640 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 265415 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 57391 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 12726 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 376344 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 707354 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2618987 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 163645 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 265416 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 57477 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 12625 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 376361 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 707361 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2618999 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 20684 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 10944 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 322592 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 665354 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 322588 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 665355 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 10806 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 5737 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 163640 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 265415 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 57391 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 12726 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 376344 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 707354 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2618987 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 163645 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 265416 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 57477 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 12625 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 376361 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 707361 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2618999 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000457 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000540 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000304 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844498 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000321 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844683 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829670 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.822884 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.834541 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.820312 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.833635 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.497223 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.452781 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.378810 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.448562 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.021516 # miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.378885 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.448589 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.021514 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.015039 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014768 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.017343 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014781 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.017348 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.029201 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.020912 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.024288 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.020926 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.024295 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000457 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.021516 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.021514 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.125852 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.015039 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.108362 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000540 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014768 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.071045 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067869 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014781 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.071063 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067876 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000457 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.021516 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.021514 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.125852 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.015039 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.108362 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000540 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014768 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.071045 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067869 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 140338.709677 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 120847.222222 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014781 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.071063 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067876 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 121815.789474 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 43274.834437 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38002.857143 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 19164.978292 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38302.857143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 19265.003615 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126170.600414 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 129572.361059 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 60847.741975 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 129566.785657 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 60848.246633 # average ReadExReq miss latency system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130352.905323 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 136253.328535 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 72065.140374 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131442.420299 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 137706.092767 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 71995.312691 # average ReadSharedReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 136435.376595 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 72159.081796 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131458.685751 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 137710.503575 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 72017.370333 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 130352.905323 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127015.785265 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 140338.709677 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 136253.328535 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 131631.123891 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 63857.823198 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 127018.392963 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 136435.376595 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 131629.001134 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 63871.541802 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 130352.905323 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127015.785265 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 140338.709677 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 136253.328535 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 131631.123891 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 63857.823198 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 127018.392963 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 136435.376595 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 131629.001134 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 63871.541802 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1609,40 +1609,40 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96355 # number of writebacks -system.l2c.writebacks::total 96355 # number of writebacks +system.l2c.writebacks::writebacks 96371 # number of writebacks +system.l2c.writebacks::total 96371 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 31 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 31 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 33 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 33 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 151 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu2.data 525 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 676 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 24150 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 37534 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 61684 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 37538 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 61688 # number of ReadExReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2461 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5557 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 8018 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5562 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 8023 # number of ReadCleanReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.data 4611 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12720 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 17331 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12729 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 17340 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 2461 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.data 28761 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 31 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5557 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 50254 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 87064 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 33 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5562 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 50267 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 87084 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 2461 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.data 28761 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 31 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5557 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 50254 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 87064 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 33 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5562 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 50267 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 87084 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable @@ -1652,114 +1652,114 @@ system.l2c.WriteReq_mshr_uncacheable::total 6370 # system.l2c.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 4040500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 4299000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10668000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 37156500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47824500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 37173000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47841000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2805520000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4488029000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7293549000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4488298000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7293818000 # number of ReadExReq MSHR miss cycles system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 296188500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 701637000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 997825500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 559971000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1624421500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 2184392500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 703281000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 999469500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 560046000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1625627000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2185673000 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 296188500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3365491000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 701637000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 6112450500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10479807500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3365566000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 703281000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 6113925000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10483259500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 296188500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3365491000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4040500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 701637000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 6112450500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10479807500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3365566000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 703281000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 6113925000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10483259500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28471375500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30579722500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 59051098000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30579727000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59051102500 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 633646000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 578928500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1212574500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 578915000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1212561000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29105021500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31158651000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60263672500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000262 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31158642000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60263663500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829670 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.822884 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.408213 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.820312 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.407474 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452781 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378810 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.212834 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378885 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.212854 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009301 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021742 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020912 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012854 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020926 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012860 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.071063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033251 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014766 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.071045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033243 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 130338.709677 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.071063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033251 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 130272.727273 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70774.285714 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70746.301775 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70805.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70770.710059 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119572.361059 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 118240.532391 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119566.785657 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118237.226041 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124448.179097 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121442.420299 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127706.092767 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126039.611101 # average ReadSharedReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124575.532843 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121458.685751 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127710.503575 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126048.039216 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117018.392963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121629.001134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 120381.005696 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117015.785265 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130338.709677 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126261.831924 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121631.123891 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 120369.010153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117018.392963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121629.001134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 120381.005696 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.775870 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.153512 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.799124 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.165679 # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201296.418637 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190357.064364 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201291.724618 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190354.945055 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.551431 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.852761 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.505606 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.828839 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 5063565 # Transaction distribution -system.membus.trans_dist::ReadResp 5112222 # Transaction distribution +system.membus.trans_dist::ReadResp 5112237 # Transaction distribution system.membus.trans_dist::WriteReq 13898 # Transaction distribution system.membus.trans_dist::WriteResp 13898 # Transaction distribution -system.membus.trans_dist::WritebackDirty 143022 # Transaction distribution -system.membus.trans_dist::CleanEvict 8552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1672 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1672 # Transaction distribution -system.membus.trans_dist::ReadExReq 129713 # Transaction distribution -system.membus.trans_dist::ReadExResp 129713 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48657 # Transaction distribution +system.membus.trans_dist::WritebackDirty 143038 # Transaction distribution +system.membus.trans_dist::CleanEvict 8555 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1675 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1675 # Transaction distribution +system.membus.trans_dist::ReadExReq 129715 # Transaction distribution +system.membus.trans_dist::ReadExResp 129715 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48672 # Transaction distribution system.membus.trans_dist::MessageReq 1644 # Transaction distribution system.membus.trans_dist::MessageResp 1644 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution @@ -1768,45 +1768,45 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_sla system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462447 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10617373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10617431 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10762648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10762706 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17501760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27151569 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17503808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27153617 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30183297 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 664 # Total snoops (count) -system.membus.snoop_fanout::samples 5457993 # Request fanout histogram +system.membus.pkt_size::total 30185345 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 665 # Total snoops (count) +system.membus.snoop_fanout::samples 5458032 # Request fanout histogram system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5456349 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::1 5456388 99.97% 99.97% # Request fanout histogram system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5457993 # Request fanout histogram -system.membus.reqLayer0.occupancy 219248500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5458032 # Request fanout histogram +system.membus.reqLayer0.occupancy 219245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2377080 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2376580 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 547350354 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 547442853 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1398080 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1397580 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1208209380 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1208317879 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 52355698 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 52360943 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1820,60 +1820,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5045321 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2544604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1171 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1171 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5045447 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2544703 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1173 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1173 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5213952 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7425084 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 5213999 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7425168 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1631207 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 861736 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 94941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1656 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1656 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289822 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289822 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 862602 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1349057 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1631215 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861756 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 94957 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289813 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289813 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862620 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1349075 # Transaction distribution system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586927 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072185 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70382 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 205946 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17935440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110356800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581265 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 259408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748104 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 324945577 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 226314 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8918759 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.005043 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.070832 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586983 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072215 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70159 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 206201 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17935558 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110359232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581393 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 258600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324948017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 226396 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8918852 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.005051 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.070893 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8873785 99.50% 99.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 44974 0.50% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8873800 99.49% 99.49% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 45052 0.51% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8918759 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3217757998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8918852 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3217820998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 405376 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 406876 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 810539408 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 810576399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1832719254 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1832733252 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24003478 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23881478 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 87328075 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 87500568 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 155f186f5..8fb0d8fd0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403830 # Number of seconds simulated -sim_ticks 403830091000 # Number of ticks simulated -final_tick 403830091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403730 # Number of seconds simulated +sim_ticks 403729503000 # Number of ticks simulated +final_tick 403729503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95719 # Simulator instruction rate (inst/s) -host_op_rate 176996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46747318 # Simulator tick rate (ticks/s) -host_mem_usage 431916 # Number of bytes of host memory used -host_seconds 8638.57 # Real time elapsed on the host +host_inst_rate 76742 # Simulator instruction rate (inst/s) +host_op_rate 141905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37470018 # Simulator tick rate (ticks/s) +host_mem_usage 427104 # Number of bytes of host memory used +host_seconds 10774.73 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24545280 # Number of bytes read from this memory -system.physmem.bytes_read::total 24709056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory -system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383520 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386079 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 405557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60781206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61186763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 405557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 405557 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46778168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46778168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46778168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 405557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60781206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107964931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386079 # Number of read requests accepted -system.physmem.writeReqs 295163 # Number of write requests accepted -system.physmem.readBursts 386079 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24689408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue -system.physmem.bytesWritten 18889088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24709056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24543168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24706880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18889152 # Number of bytes written to this memory +system.physmem.bytes_written::total 18889152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383487 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386045 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295143 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295143 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 405499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60791118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61196618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 405499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 405499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46786653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46786653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46786653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 405499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60791118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107983270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386045 # Number of read requests accepted +system.physmem.writeReqs 295143 # Number of write requests accepted +system.physmem.readBursts 386045 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24687936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18944 # Total number of bytes read from write queue +system.physmem.bytesWritten 18887232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24706880 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18889152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 296 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 251728 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 250871 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 24087 # Per bank write bursts -system.physmem.perBankRdBursts::1 26440 # Per bank write bursts -system.physmem.perBankRdBursts::2 24835 # Per bank write bursts -system.physmem.perBankRdBursts::3 24498 # Per bank write bursts -system.physmem.perBankRdBursts::4 23219 # Per bank write bursts -system.physmem.perBankRdBursts::5 23721 # Per bank write bursts -system.physmem.perBankRdBursts::6 24501 # Per bank write bursts -system.physmem.perBankRdBursts::7 24288 # Per bank write bursts +system.physmem.perBankRdBursts::1 26442 # Per bank write bursts +system.physmem.perBankRdBursts::2 24836 # Per bank write bursts +system.physmem.perBankRdBursts::3 24492 # Per bank write bursts +system.physmem.perBankRdBursts::4 23224 # Per bank write bursts +system.physmem.perBankRdBursts::5 23711 # Per bank write bursts +system.physmem.perBankRdBursts::6 24489 # Per bank write bursts +system.physmem.perBankRdBursts::7 24279 # Per bank write bursts system.physmem.perBankRdBursts::8 23633 # Per bank write bursts -system.physmem.perBankRdBursts::9 23532 # Per bank write bursts -system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::9 23527 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts system.physmem.perBankRdBursts::11 23996 # Per bank write bursts -system.physmem.perBankRdBursts::12 23302 # Per bank write bursts -system.physmem.perBankRdBursts::13 22925 # Per bank write bursts -system.physmem.perBankRdBursts::14 24085 # Per bank write bursts -system.physmem.perBankRdBursts::15 23896 # Per bank write bursts -system.physmem.perBankWrBursts::0 18615 # Per bank write bursts +system.physmem.perBankRdBursts::12 23303 # Per bank write bursts +system.physmem.perBankRdBursts::13 22926 # Per bank write bursts +system.physmem.perBankRdBursts::14 24088 # Per bank write bursts +system.physmem.perBankRdBursts::15 23899 # Per bank write bursts +system.physmem.perBankWrBursts::0 18617 # Per bank write bursts system.physmem.perBankWrBursts::1 19935 # Per bank write bursts -system.physmem.perBankWrBursts::2 19196 # Per bank write bursts -system.physmem.perBankWrBursts::3 19026 # Per bank write bursts -system.physmem.perBankWrBursts::4 18118 # Per bank write bursts -system.physmem.perBankWrBursts::5 18514 # Per bank write bursts -system.physmem.perBankWrBursts::6 19142 # Per bank write bursts -system.physmem.perBankWrBursts::7 19086 # Per bank write bursts -system.physmem.perBankWrBursts::8 18651 # Per bank write bursts -system.physmem.perBankWrBursts::9 17953 # Per bank write bursts +system.physmem.perBankWrBursts::2 19195 # Per bank write bursts +system.physmem.perBankWrBursts::3 19025 # Per bank write bursts +system.physmem.perBankWrBursts::4 18116 # Per bank write bursts +system.physmem.perBankWrBursts::5 18510 # Per bank write bursts +system.physmem.perBankWrBursts::6 19136 # Per bank write bursts +system.physmem.perBankWrBursts::7 19083 # Per bank write bursts +system.physmem.perBankWrBursts::8 18650 # Per bank write bursts +system.physmem.perBankWrBursts::9 17952 # Per bank write bursts system.physmem.perBankWrBursts::10 18925 # Per bank write bursts -system.physmem.perBankWrBursts::11 17775 # Per bank write bursts +system.physmem.perBankWrBursts::11 17774 # Per bank write bursts system.physmem.perBankWrBursts::12 17401 # Per bank write bursts -system.physmem.perBankWrBursts::13 17016 # Per bank write bursts -system.physmem.perBankWrBursts::14 17907 # Per bank write bursts -system.physmem.perBankWrBursts::15 17882 # Per bank write bursts +system.physmem.perBankWrBursts::13 17014 # Per bank write bursts +system.physmem.perBankWrBursts::14 17904 # Per bank write bursts +system.physmem.perBankWrBursts::15 17876 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403830049500 # Total gap between requests +system.physmem.totGap 403729461000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386079 # Read request sizes (log2) +system.physmem.readPktSize::6 386045 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295143 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,31 +144,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16966 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17703 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17900 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 17614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see @@ -193,41 +193,40 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146827 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.793805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.429172 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.898216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54192 36.91% 36.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39812 27.11% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13750 9.36% 73.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7660 5.22% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5440 3.71% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4000 2.72% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3009 2.05% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2793 1.90% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16171 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146827 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17508 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.033813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.830406 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.850108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.490764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.864709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54135 36.88% 36.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39792 27.11% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13762 9.38% 73.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7666 5.22% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5518 3.76% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3980 2.71% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2950 2.01% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16189 11.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146786 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.035647 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.931424 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17508 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17508 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.857551 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.779124 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.831180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17335 99.01% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 121 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.858783 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.780497 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.828638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17323 98.96% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 130 0.74% 99.70% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 8 0.05% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads @@ -239,202 +238,202 @@ system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17508 # Writes before turning the bus around for reads -system.physmem.totQLat 4276128000 # Total ticks spent queuing -system.physmem.totMemAccLat 11509353000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928860000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11084.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads +system.physmem.totQLat 4275493000 # Total ticks spent queuing +system.physmem.totMemAccLat 11508286750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11083.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29834.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.77 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29833.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing -system.physmem.readRowHits 318168 # Number of row buffer hits during reads -system.physmem.writeRowHits 215906 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 592785.02 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567876960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309853500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1525477200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982432800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62051510430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187864648500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279677755230 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.569390 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311979208000 # Time in different power states -system.physmem_0.memoryStateTime::REF 13484640000 # Time in different power states +system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing +system.physmem.readRowHits 318194 # Number of row buffer hits during reads +system.physmem.writeRowHits 215867 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.14 # Row buffer hit rate for writes +system.physmem.avgGap 592684.34 # Average gap between requests +system.physmem.pageHitRate 78.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567559440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309680250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525227600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982283760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26369344560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61980966945 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187865787750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279600850305 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.552566 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311981579750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13481260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78362495750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78262397250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 541779840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295614000 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 541772280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295609875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1483021800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929672640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60320910060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189382719000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279329673180 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.707431 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314516116250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13484640000 # Time in different power states +system.physmem_1.writeEnergy 929607840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26369344560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60334101000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189310415250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279263872605 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.717871 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314398189250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13481260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75825587500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75845673250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219264229 # Number of BP lookups -system.cpu.branchPred.condPredicted 219264229 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8531047 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 124002696 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121802201 # Number of BTB hits +system.cpu.branchPred.lookups 219274987 # Number of BP lookups +system.cpu.branchPred.condPredicted 219274987 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8531522 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 123993741 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121807441 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.225446 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27063113 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406921 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.236766 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27065979 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406611 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807660183 # number of cpu cycles simulated +system.cpu.numCycles 807459007 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175911242 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208663462 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219264229 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148865314 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621862787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17775835 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 233 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 94904 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 745978 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1264 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170762091 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2319100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 175909904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208657074 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219274987 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148873420 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621672943 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17773933 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 228 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 93572 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 739186 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1184 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170767375 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2320347 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807504342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.785127 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 807304003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.785786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367608 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417532473 51.71% 51.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32497368 4.02% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31891068 3.95% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32657877 4.04% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26554759 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26902865 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35168137 4.36% 74.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31391832 3.89% 78.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172907963 21.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417240348 51.68% 51.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32574428 4.03% 55.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31907657 3.95% 59.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32681653 4.05% 63.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26580392 3.29% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26881376 3.33% 70.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35152240 4.35% 74.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31387341 3.89% 78.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172898568 21.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807504342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271481 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496500 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120449956 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370877919 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225251519 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82037031 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8887917 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132109647 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8887917 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152555499 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150771591 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44475 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271462113 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223782747 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088438662 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 138448 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138151621 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24868058 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50731794 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190645258 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278038161 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357041251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59967 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807304003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271562 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120520385 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370608769 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225149515 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82138368 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8886966 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132102743 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8886966 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152568309 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150685768 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 43752 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271514393 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223604815 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088452096 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 136935 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138015544 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24816035 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50717991 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190623283 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5277995133 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3356987177 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59736 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576604404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3331 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3057 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422478077 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507119798 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200816388 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229077730 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68200212 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023068034 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22911 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1788999576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 413303 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494102244 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 832764755 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22359 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807504342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.215467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.071001 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576582429 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3320 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3053 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422372622 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507122898 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200817266 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229152229 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68250410 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023093893 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22490 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1789041324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 413281 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494127682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832693724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 21938 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807304003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.216069 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.071086 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238908265 29.59% 29.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123628552 15.31% 44.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118817632 14.71% 59.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107769877 13.35% 72.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89573603 11.09% 84.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60241832 7.46% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42310466 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18973159 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7280956 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238827775 29.58% 29.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123535270 15.30% 44.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118660489 14.70% 59.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107754933 13.35% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89757341 11.12% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60254934 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42261668 5.23% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18966509 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7285084 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807504342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807304003 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11498712 42.77% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12295029 45.73% 88.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3093590 11.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11494986 42.61% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12377047 45.88% 88.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3103525 11.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718967 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183065523 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 369413 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881231 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717072 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183096351 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369503 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881165 0.22% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 133 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 60 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 59 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 366 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -456,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428545273 23.95% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170418596 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428542339 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170434336 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1788999576 # Type of FU issued -system.cpu.iq.rate 2.215040 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26887331 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015029 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412774566 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517442986 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762358918 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29562 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69250 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5611 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813154984 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12956 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186087729 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1789041324 # Type of FU issued +system.cpu.iq.rate 2.215644 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26975558 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412746171 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517494100 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762401602 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29319 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 68666 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5587 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813286934 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12876 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186139067 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123020037 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213128 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 372787 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51656202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123023226 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213197 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 372513 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51657080 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22930 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1078 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22979 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1120 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8887917 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97798502 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6162253 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023090945 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 375323 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507122194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200816388 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7129 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1832886 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3426694 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 372787 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845812 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4140641 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8986453 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1769991187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423150453 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19008389 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8886966 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97771041 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6172788 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023116383 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 372939 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507125383 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200817266 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6964 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1835087 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3428846 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 372513 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4846135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4139030 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8985165 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1770027230 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423145659 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19014094 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590375275 # number of memory reference insts executed -system.cpu.iew.exec_branches 168976940 # Number of branches executed -system.cpu.iew.exec_stores 167224822 # Number of stores executed -system.cpu.iew.exec_rate 2.191505 # Inst execution rate -system.cpu.iew.wb_sent 1766866321 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762364529 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339720871 # num instructions producing a value -system.cpu.iew.wb_consumers 2049946578 # num instructions consuming a value -system.cpu.iew.wb_rate 2.182062 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653539 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 494164798 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 590385270 # number of memory reference insts executed +system.cpu.iew.exec_branches 168978597 # Number of branches executed +system.cpu.iew.exec_stores 167239611 # Number of stores executed +system.cpu.iew.exec_rate 2.192095 # Inst execution rate +system.cpu.iew.wb_sent 1766903441 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762407189 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339775634 # num instructions producing a value +system.cpu.iew.wb_consumers 2050025380 # num instructions consuming a value +system.cpu.iew.wb_rate 2.182658 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653541 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 494189981 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8615583 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740300612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.065362 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575682 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8614804 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740092650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.065942 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.576063 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276280439 37.32% 37.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172026383 23.24% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 56011691 7.57% 68.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86227626 11.65% 79.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25892196 3.50% 83.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26512378 3.58% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9839162 1.33% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8995484 1.22% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78515253 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276159555 37.31% 37.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172046341 23.25% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55756685 7.53% 68.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86381753 11.67% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25885092 3.50% 83.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26500840 3.58% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9823966 1.33% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9011977 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78526441 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740300612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740092650 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,350 +576,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78515253 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684938858 # The number of ROB reads -system.cpu.rob.rob_writes 4113685431 # The number of ROB writes -system.cpu.timesIdled 1962 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155841 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78526441 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684744891 # The number of ROB reads +system.cpu.rob.rob_writes 4113743876 # The number of ROB writes +system.cpu.timesIdled 1971 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155004 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976760 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976760 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023793 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023793 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722687854 # number of integer regfile reads -system.cpu.int_regfile_writes 1435809850 # number of integer regfile writes -system.cpu.fp_regfile_reads 5827 # number of floating regfile reads -system.cpu.fp_regfile_writes 561 # number of floating regfile writes -system.cpu.cc_regfile_reads 596681162 # number of cc regfile reads -system.cpu.cc_regfile_writes 405470892 # number of cc regfile writes -system.cpu.misc_regfile_reads 971641846 # number of misc regfile reads +system.cpu.cpi 0.976516 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976516 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024048 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024048 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722732526 # number of integer regfile reads +system.cpu.int_regfile_writes 1435834166 # number of integer regfile writes +system.cpu.fp_regfile_reads 5786 # number of floating regfile reads +system.cpu.fp_regfile_writes 522 # number of floating regfile writes +system.cpu.cc_regfile_reads 596664701 # number of cc regfile reads +system.cpu.cc_regfile_writes 405464893 # number of cc regfile writes +system.cpu.misc_regfile_reads 971659418 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530997 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.815869 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381868965 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.633119 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530951 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.813830 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381812834 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535047 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.613710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.815869 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813830 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772828805 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772828805 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233213748 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233213748 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173817 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173817 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381387565 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381387565 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381387565 # number of overall hits -system.cpu.dcache.overall_hits::total 381387565 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2772906 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2772906 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986385 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986385 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3759291 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759291 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759291 # number of overall misses -system.cpu.dcache.overall_misses::total 3759291 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59174415500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59174415500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31292251995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31292251995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90466667495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90466667495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90466667495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90466667495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235986654 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235986654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772716551 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772716551 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233156746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233156746 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148174671 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148174671 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381331417 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381331417 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381331417 # number of overall hits +system.cpu.dcache.overall_hits::total 381331417 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2773804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2773804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 985531 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 985531 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3759335 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3759335 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759335 # number of overall misses +system.cpu.dcache.overall_misses::total 3759335 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59185001500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59185001500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31266038497 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31266038497 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90451039997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90451039997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90451039997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90451039997 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235930550 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235930550 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385146856 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385146856 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385146856 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385146856 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009761 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009761 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009761 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009761 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24064.821663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24064.821663 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9788 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385090752 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385090752 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385090752 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385090752 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011757 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011757 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006607 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009762 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009762 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21337.124577 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21337.124577 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.068513 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.068513 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24060.383019 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24060.383019 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24060.383019 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24060.383019 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9981 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1062 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.348615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.398305 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330532 # number of writebacks -system.cpu.dcache.writebacks::total 2330532 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007920 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1007920 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19403 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19403 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1027323 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1027323 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1027323 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1027323 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966982 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 966982 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2731968 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2731968 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2731968 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2731968 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33558631000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33558631000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30070164497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30070164497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63628795497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63628795497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63628795497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63628795497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330539 # number of writebacks +system.cpu.dcache.writebacks::total 2330539 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1008865 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1008865 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19395 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19395 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1028260 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1028260 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1028260 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1028260 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764939 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764939 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966136 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 966136 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2731075 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2731075 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2731075 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2731075 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33555381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33555381500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30045027999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30045027999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63600409499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63600409499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63600409499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63600409499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007092 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007092 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007092 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007092 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19012.204671 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19012.204671 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31098.135251 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31098.135251 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23287.683238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23287.683238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23287.683238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23287.683238 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6653 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.717066 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170551460 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8264 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20637.882381 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6666 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.069006 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170557949 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8273 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20616.215279 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.717066 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506698 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506698 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 321 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1160 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341729418 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341729418 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170554639 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170554639 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170554639 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170554639 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170554639 # number of overall hits -system.cpu.icache.overall_hits::total 170554639 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 207451 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 207451 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 207451 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 207451 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 207451 # number of overall misses -system.cpu.icache.overall_misses::total 207451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1211820000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1211820000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1211820000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1211820000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1211820000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1211820000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170762090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170762090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170762090 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170762090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170762090 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170762090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001215 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001215 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001215 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001215 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001215 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001215 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5841.475818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5841.475818 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5841.475818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5841.475818 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 674 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.069006 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506381 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506381 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1154 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341739161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341739161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170560782 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170560782 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170560782 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170560782 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170560782 # number of overall hits +system.cpu.icache.overall_hits::total 170560782 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 206592 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 206592 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 206592 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 206592 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 206592 # number of overall misses +system.cpu.icache.overall_misses::total 206592 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1205108500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1205108500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1205108500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1205108500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1205108500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1205108500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170767374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170767374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170767374 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170767374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170767374 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170767374 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001210 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001210 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001210 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001210 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001210 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001210 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5833.277668 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5833.277668 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5833.277668 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5833.277668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5833.277668 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5833.277668 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1131 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 74.888889 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 113.100000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 6653 # number of writebacks -system.cpu.icache.writebacks::total 6653 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2211 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2211 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2211 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2211 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2211 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205240 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205240 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205240 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205240 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205240 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205240 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 926829000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 926829000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 926829000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 926829000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 926829000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 926829000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4515.830248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4515.830248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6666 # number of writebacks +system.cpu.icache.writebacks::total 6666 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2177 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2177 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2177 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2177 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2177 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2177 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 204415 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 204415 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 204415 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 204415 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 204415 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 204415 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 920446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 920446000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 920446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 920446000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 920446000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 920446000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001197 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001197 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001197 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001197 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001197 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001197 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4502.830027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4502.830027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4502.830027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4502.830027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4502.830027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4502.830027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 355338 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29622.648539 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3892669 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387670 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.041192 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 355303 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29622.252960 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3892821 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 387635 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.042491 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 189329679500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21024.249099 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.226961 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8412.172479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.641609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.256719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.904011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 21027.619838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.034740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8408.598382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.641712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005677 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.256610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903999 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32332 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18619 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13401 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18616 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986694 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43294553 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43294553 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2330532 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2330532 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6263 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6263 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563568 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563568 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5677 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5677 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587956 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587956 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5677 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151524 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2157201 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5677 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151524 # number of overall hits -system.cpu.l2cache.overall_hits::total 2157201 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 195036 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 195036 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206929 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206929 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2561 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2561 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176640 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176640 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383569 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386130 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2561 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383569 # number of overall misses -system.cpu.l2cache.overall_misses::total 386130 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13989000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13989000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16413605500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16413605500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 209990000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 209990000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14188998500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14188998500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 209990000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30602604000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30812594000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 209990000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30602604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30812594000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330532 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2330532 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6263 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6263 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196875 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 196875 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.tag_accesses 43287155 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43287155 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2330539 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2330539 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6254 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6254 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1848 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1848 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 563570 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 563570 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5700 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587937 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1587937 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151507 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2157207 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5700 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151507 # number of overall hits +system.cpu.l2cache.overall_hits::total 2157207 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 194180 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 194180 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206927 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206927 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2560 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2560 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176613 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 176613 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2560 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383540 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386100 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2560 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383540 # number of overall misses +system.cpu.l2cache.overall_misses::total 386100 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14120500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 14120500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16416663000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16416663000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 207070000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 207070000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14186015000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14186015000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30602678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30809748000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30602678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30809748000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330539 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2330539 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6254 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6254 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196028 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 196028 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 770497 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 770497 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8238 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8238 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764596 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1764596 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8238 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2535093 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8238 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2535093 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990659 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990659 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268566 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268566 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.310876 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.310876 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100102 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100102 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.310876 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151821 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.310876 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151821 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 71.725220 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 71.725220 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79319.986565 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79319.986565 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81995.314330 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81995.314330 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80327.210711 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80327.210711 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81995.314330 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79783.830289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79798.497915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81995.314330 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79783.830289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79798.497915 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8260 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8260 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764550 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1764550 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8260 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2535047 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2543307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8260 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2535047 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2543307 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990573 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990573 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268563 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268563 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.309927 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.309927 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100090 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100090 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.309927 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151295 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151810 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.309927 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151295 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151810 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.718612 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.718612 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79335.528955 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79335.528955 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80886.718750 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80886.718750 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80322.597997 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80322.597997 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80886.718750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79790.055796 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79797.327117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80886.718750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79790.055796 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79797.327117 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -929,8 +928,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks -system.cpu.l2cache.writebacks::total 295163 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 295143 # number of writebacks +system.cpu.l2cache.writebacks::total 295143 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits @@ -939,133 +938,133 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195036 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 195036 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206929 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206929 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2560 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2560 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176640 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176640 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2560 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383569 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386129 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2560 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383569 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386129 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4301153024 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4301153024 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344315500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344315500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184333500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184333500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12422598500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12422598500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184333500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26766914000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26951247500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184333500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26766914000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26951247500 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 194180 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 194180 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206927 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206927 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176613 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176613 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383540 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386099 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383540 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386099 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4282767398 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4282767398 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14347393000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14347393000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181423500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181423500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12419885000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12419885000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181423500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26767278000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26948701500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181423500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26767278000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26948701500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990659 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990659 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268566 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310755 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151820 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151820 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990573 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990573 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268563 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268563 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.309806 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.309806 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100090 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100090 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.309806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151295 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151810 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.309806 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151295 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151810 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22055.656597 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22055.656597 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69335.528955 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69335.528955 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70896.248535 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70896.248535 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70322.597997 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70322.597997 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70896.248535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69790.055796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69797.387458 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70896.248535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69790.055796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69797.387458 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5474858 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731062 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212394 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3599 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3599 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5473107 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2730253 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 211507 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3590 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1969834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2625695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6263 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 249937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196875 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1968963 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 770497 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 770497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 205240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764596 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219739 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7984230 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8203969 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 927936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311400000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312327936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552340 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3292546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.124310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.329935 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 204415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764550 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218927 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7982402 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8201329 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 928768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311397504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312326272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 551458 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3290793 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.123868 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329431 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2883249 87.57% 87.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 409297 12.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883170 87.61% 87.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 407623 12.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3292546 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5102581952 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3290793 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5101790823 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 307865483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 306628981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3901080066 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3900587569 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179198 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution -system.membus.trans_dist::CleanEvict 56643 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195085 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195085 # Transaction distribution -system.membus.trans_dist::ReadExReq 206880 # Transaction distribution -system.membus.trans_dist::ReadExResp 206880 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179199 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1514133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43599424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43599424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179170 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295143 # Transaction distribution +system.membus.trans_dist::CleanEvict 56638 # Transaction distribution +system.membus.trans_dist::UpgradeReq 194233 # Transaction distribution +system.membus.trans_dist::UpgradeResp 194233 # Transaction distribution +system.membus.trans_dist::ReadExReq 206874 # Transaction distribution +system.membus.trans_dist::ReadExResp 206874 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179171 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1512336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1512336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1512336 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43595968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43595968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43595968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 932970 # Request fanout histogram +system.membus.snoop_fanout::samples 932059 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 932970 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 932059 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 932970 # Request fanout histogram -system.membus.reqLayer0.occupancy 2244779968 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 932059 # Request fanout histogram +system.membus.reqLayer0.occupancy 2243503595 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2432276830 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2430366430 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |