diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
| commit | 85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch) | |
| tree | bc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/long | |
| parent | 21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff) | |
| download | gem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz | |
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/long')
72 files changed, 2959 insertions, 360 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 2f001f46a..ba2f5bb49 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.907083 # Nu sim_ticks 1907083088000 # Number of ticks simulated final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20329 # Simulator instruction rate (inst/s) -host_op_rate 20329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 690572794 # Simulator tick rate (ticks/s) -host_mem_usage 384580 # Number of bytes of host memory used -host_seconds 2761.60 # Real time elapsed on the host +host_inst_rate 17729 # Simulator instruction rate (inst/s) +host_op_rate 17729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 602270723 # Simulator tick rate (ticks/s) +host_mem_usage 432228 # Number of bytes of host memory used +host_seconds 3166.49 # Real time elapsed on the host sim_insts 56139550 # Number of instructions simulated sim_ops 56139550 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1045632 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24852608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -299,6 +300,8 @@ system.physmem_1.memoryStateTime::REF 63681540000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 40135521250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 15213605 # Number of BP lookups system.cpu.branchPred.condPredicted 13089935 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 512661 # Number of conditional branches incorrect @@ -345,6 +348,16 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281609048.541405 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439540029.573258 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 10500 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 111543794500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1795539293500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 223105667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -477,6 +490,7 @@ system.cpu.kern.mode_ticks::idle 1863670965500 97.72% 100.00% # n system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.tickCycles 85299333 # Number of cycles that the object actually ticked system.cpu.idleCycles 137806334 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1394573 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976747 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 13828974 # Total number of references to valid blocks. @@ -493,6 +507,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 63880747 # Number of tag accesses system.cpu.dcache.tags.data_accesses 63880747 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 7869575 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7869575 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5576818 # number of WriteReq hits @@ -629,6 +644,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1471396 # number of replacements system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. @@ -645,6 +661,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 405 system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 22083145 # Number of tag accesses system.cpu.icache.tags.data_accesses 22083145 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 19138985 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 19138985 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 19138985 # number of demand (read+write) hits @@ -713,6 +730,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 339491 # number of replacements system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. @@ -735,6 +753,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55510 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 46558497 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 46558497 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 837991 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 837991 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1470820 # number of WritebackClean hits @@ -911,6 +930,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 system.cpu.toL2Bus.snoop_filter.tot_snoops 1250 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2570147 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution @@ -964,6 +984,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1018,6 +1039,7 @@ system.iobus.respLayer0.occupancy 23483000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.298739 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1032,6 +1054,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1112,6 +1135,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 295608 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution @@ -1160,6 +1184,11 @@ system.membus.respLayer1.occupancy 2159448000 # La system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1191,5 +1220,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907083088000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 7d7e06664..0eee642ef 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.908652 # Nu sim_ticks 1908652088000 # Number of ticks simulated final_tick 1908652088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169428 # Simulator instruction rate (inst/s) -host_op_rate 169428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5757307258 # Simulator tick rate (ticks/s) -host_mem_usage 336708 # Number of bytes of host memory used -host_seconds 331.52 # Real time elapsed on the host +host_inst_rate 205918 # Simulator instruction rate (inst/s) +host_op_rate 205918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6997264233 # Simulator tick rate (ticks/s) +host_mem_usage 384940 # Number of bytes of host memory used +host_seconds 272.77 # Real time elapsed on the host sim_insts 56168509 # Number of instructions simulated sim_ops 56168509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 873216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24648192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 103232 # Number of bytes read from this memory @@ -324,6 +325,8 @@ system.physmem_1.memoryStateTime::REF 63734060000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 23527607250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.branchPred.lookups 18555851 # Number of BP lookups system.cpu0.branchPred.condPredicted 15805635 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 543843 # Number of conditional branches incorrect @@ -370,6 +373,17 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.numPwrStateTransitions 12751 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 289891468.868256 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 443092480.248663 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 4 0.06% 0.06% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6372 99.94% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 60304082496 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1848348005504 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 120614537 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -665,6 +679,7 @@ system.cpu0.fp_regfile_reads 142673 # nu system.cpu0.fp_regfile_writes 153221 # number of floating regfile writes system.cpu0.misc_regfile_reads 1866400 # number of misc regfile reads system.cpu0.misc_regfile_writes 877434 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 1337856 # number of replacements system.cpu0.dcache.tags.tagsinuse 505.906059 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 11855471 # Total number of references to valid blocks. @@ -680,6 +695,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::3 4 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 62973100 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 62973100 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 7528886 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7528886 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3919891 # number of WriteReq hits @@ -832,6 +848,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222625.620303 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222625.620303 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93130.397390 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93130.397390 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1021310 # number of replacements system.cpu0.icache.tags.tagsinuse 509.519684 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 8197716 # Total number of references to valid blocks. @@ -847,6 +864,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 20 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 10303980 # Number of tag accesses system.cpu0.icache.tags.data_accesses 10303980 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 8197716 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 8197716 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 8197716 # number of demand (read+write) hits @@ -966,6 +984,16 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.numPwrStateTransitions 4618 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2309 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 824384353.183196 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 333980461.680684 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2309 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 88500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 975572500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2309 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 5148616500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1903503471500 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 10299543 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1260,6 +1288,7 @@ system.cpu1.fp_regfile_reads 26922 # nu system.cpu1.fp_regfile_writes 25344 # number of floating regfile writes system.cpu1.misc_regfile_reads 302216 # number of misc regfile reads system.cpu1.misc_regfile_writes 137559 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 64410 # number of replacements system.cpu1.dcache.tags.tagsinuse 463.614906 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 1794834 # Total number of references to valid blocks. @@ -1276,6 +1305,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 8336582 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 8336582 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 1188882 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1188882 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 570377 # number of WriteReq hits @@ -1436,6 +1466,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202982.876712 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202982.876712 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10855.494505 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10855.494505 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 125381 # number of replacements system.cpu1.icache.tags.tagsinuse 466.454678 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 1056750 # Total number of references to valid blocks. @@ -1453,6 +1484,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 1315314 # Number of tag accesses system.cpu1.icache.tags.data_accesses 1315314 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 1056751 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 1056751 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 1056751 # number of demand (read+write) hits @@ -1539,6 +1571,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7381 # Transaction distribution system.iobus.trans_dist::ReadResp 7381 # Transaction distribution system.iobus.trans_dist::WriteReq 53943 # Transaction distribution @@ -1593,6 +1626,7 @@ system.iobus.respLayer0.occupancy 26789000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41964000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41702 # number of replacements system.iocache.tags.tagsinuse 0.516326 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1607,6 +1641,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375606 # Number of tag accesses system.iocache.tags.data_accesses 375606 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 182 # number of ReadReq misses system.iocache.ReadReq_misses::total 182 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1687,6 +1722,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66945.590885 system.iocache.demand_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66945.590885 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 66945.590885 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 344399 # number of replacements system.l2c.tags.tagsinuse 65257.528904 # Cycle average of tags in use system.l2c.tags.total_refs 4049043 # Total number of references to valid blocks. @@ -1713,6 +1749,7 @@ system.l2c.tags.age_task_id_blocks_1024::4 51897 # system.l2c.tags.occ_task_id_percent::1024 0.991791 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 38854214 # Number of tag accesses system.l2c.tags.data_accesses 38854214 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 830750 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 830750 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 873391 # number of WritebackClean hits @@ -2019,6 +2056,7 @@ system.membus.snoop_filter.hit_multi_requests 439 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7199 # Transaction distribution system.membus.trans_dist::ReadResp 297053 # Transaction distribution system.membus.trans_dist::WriteReq 12391 # Transaction distribution @@ -2068,12 +2106,14 @@ system.membus.respLayer1.occupancy 2171993250 # La system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 976613 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 5115302 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 2557070 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 337938 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1067 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2263337 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 12391 # Transaction distribution @@ -2128,6 +2168,10 @@ system.toL2Bus.respLayer2.occupancy 190444943 # La system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer3.occupancy 107558787 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2159,6 +2203,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1908652088000 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6376 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 198541 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 9b89e5da4..cd56250dd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.876794 # Nu sim_ticks 1876794488000 # Number of ticks simulated final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156335 # Simulator instruction rate (inst/s) -host_op_rate 156335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5537786455 # Simulator tick rate (ticks/s) -host_mem_usage 329540 # Number of bytes of host memory used -host_seconds 338.91 # Real time elapsed on the host +host_inst_rate 191271 # Simulator instruction rate (inst/s) +host_op_rate 191271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6775305946 # Simulator tick rate (ticks/s) +host_mem_usage 377772 # Number of bytes of host memory used +host_seconds 277.01 # Real time elapsed on the host sim_insts 52982943 # Number of instructions simulated sim_ops 52982943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 961728 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory @@ -298,6 +299,8 @@ system.physmem_1.memoryStateTime::REF 62670140000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 30709733500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 19569408 # Number of BP lookups system.cpu.branchPred.condPredicted 16632311 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 593173 # Number of conditional branches incorrect @@ -344,6 +347,16 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numPwrStateTransitions 12876 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6438 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279467835.818577 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439243252.658256 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6438 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 81000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 6438 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 77580561000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1799213927000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 155167561 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -640,6 +653,7 @@ system.cpu.fp_regfile_reads 166613 # nu system.cpu.fp_regfile_writes 175794 # number of floating regfile writes system.cpu.misc_regfile_reads 2001927 # number of misc regfile reads system.cpu.misc_regfile_writes 939529 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1405900 # number of replacements system.cpu.dcache.tags.tagsinuse 511.992670 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 12627832 # Total number of references to valid blocks. @@ -656,6 +670,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 41 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 67144149 # Number of tag accesses system.cpu.dcache.tags.data_accesses 67144149 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 8017767 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 8017767 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4181578 # number of WriteReq hits @@ -808,6 +823,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1074186 # number of replacements system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. @@ -824,6 +840,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 366 system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11005600 # Number of tag accesses system.cpu.icache.tags.data_accesses 11005600 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 8786985 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 8786985 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 8786985 # number of demand (read+write) hits @@ -898,6 +915,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 338591 # number of replacements system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. @@ -920,6 +938,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55427 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 40379667 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 40379667 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 843569 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 843569 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1073682 # number of WritebackClean hits @@ -1116,6 +1135,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2188672 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution @@ -1170,6 +1190,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1224,6 +1245,7 @@ system.iobus.respLayer0.occupancy 23459000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.249213 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1238,6 +1260,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1318,6 +1341,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 296606 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution @@ -1367,6 +1391,11 @@ system.membus.respLayer1.occupancy 2138626000 # La system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 918617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1398,6 +1427,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1876794488000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6438 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211036 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index f41b81651..d2e8a2346 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.841599 # Nu sim_ticks 1841599161000 # Number of ticks simulated final_tick 1841599161000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245408 # Simulator instruction rate (inst/s) -host_op_rate 245408 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6773643024 # Simulator tick rate (ticks/s) -host_mem_usage 331844 # Number of bytes of host memory used -host_seconds 271.88 # Real time elapsed on the host +host_inst_rate 307539 # Simulator instruction rate (inst/s) +host_op_rate 307539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8488565495 # Simulator tick rate (ticks/s) +host_mem_usage 380848 # Number of bytes of host memory used +host_seconds 216.95 # Real time elapsed on the host sim_insts 66720805 # Number of instructions simulated sim_ops 66720805 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 472448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20115392 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory @@ -330,6 +331,8 @@ system.physmem_1.memoryStateTime::REF 45531980000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 8896844750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -363,6 +366,16 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.numPwrStateTransitions 6508 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 3254 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 553026714.363860 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 1352809149.832599 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3254 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 213500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 3905515000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 3254 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 42050232460 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1799548928540 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 928788202 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -506,6 +519,7 @@ system.cpu0.op_class::MemWrite 3423231 11.40% 98.28% # Cl system.cpu0.op_class::IprAccess 516318 1.72% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 30035361 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 1394566 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 13521910 # Total number of references to valid blocks. @@ -526,6 +540,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 64423039 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 64423039 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 3984765 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1069804 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 2772856 # number of ReadReq hits @@ -761,6 +776,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218663.747811 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 97107.965638 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 99971.120575 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 98810.541311 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 969876 # number of replacements system.cpu0.icache.tags.tagsinuse 511.205246 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 39683030 # Total number of references to valid blocks. @@ -781,6 +797,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 41646260 # Number of tag accesses system.cpu0.icache.tags.data_accesses 41646260 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 29526010 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 7417850 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2739170 # number of ReadReq hits @@ -929,6 +946,16 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.numPwrStateTransitions 2293 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1147 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1553407081.081081 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 1902806399.455202 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1147 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 6635637500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1147 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 59841239000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1781757922000 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 953375365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1049,6 +1076,16 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses +system.cpu2.numPwrStateTransitions 3116 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 1558 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 289379505.134788 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 445107312.150922 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 1558 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 3000 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 1558 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 1390745892000 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 450853269000 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 30327275 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1358,6 +1395,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution system.iobus.trans_dist::WriteReq 51362 # Transaction distribution @@ -1404,6 +1442,7 @@ system.iobus.respLayer0.occupancy 9173000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.254561 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1418,6 +1457,7 @@ system.iocache.tags.age_task_id_blocks_1023::2 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1498,6 +1538,7 @@ system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66910.723631 system.iocache.demand_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66910.723631 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 66910.723631 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 337756 # number of replacements system.l2c.tags.tagsinuse 65421.322565 # Cycle average of tags in use system.l2c.tags.total_refs 4020988 # Total number of references to valid blocks. @@ -1528,6 +1569,7 @@ system.l2c.tags.age_task_id_blocks_1024::4 55336 # system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 38533534 # Number of tag accesses system.l2c.tags.data_accesses 38533534 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 836681 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 836681 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 969577 # number of WritebackClean hits @@ -1838,6 +1880,7 @@ system.membus.snoop_filter.hit_multi_requests 408 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7144 # Transaction distribution system.membus.trans_dist::ReadResp 295138 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution @@ -1888,12 +1931,14 @@ system.membus.respLayer1.occupancy 436169750 # La system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 370538 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 4730181 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 2364664 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1038 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1038 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2070392 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution @@ -1936,6 +1981,10 @@ system.toL2Bus.respLayer0.occupancy 692196311 # La system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 770446828 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1967,6 +2016,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1841599161000 # Cumulative time (in ticks) in various power states system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index e76fc661c..8a8cb49d0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.847227 # Nu sim_ticks 2847227406000 # Number of ticks simulated final_tick 2847227406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111277 # Simulator instruction rate (inst/s) -host_op_rate 134747 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2488466073 # Simulator tick rate (ticks/s) -host_mem_usage 617520 # Number of bytes of host memory used -host_seconds 1144.17 # Real time elapsed on the host +host_inst_rate 262523 # Simulator instruction rate (inst/s) +host_op_rate 317894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5870765699 # Simulator tick rate (ticks/s) +host_mem_usage 664268 # Number of bytes of host memory used +host_seconds 484.98 # Real time elapsed on the host sim_insts 127319545 # Number of instructions simulated sim_ops 154173476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 7488 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1647744 # Number of bytes read from this memory @@ -341,6 +342,7 @@ system.physmem_1.memoryStateTime::REF 95074980000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 31288281989 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -359,6 +361,9 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -379,6 +384,7 @@ system.cpu0.branchPred.indirectHits 581758 # Nu system.cpu0.branchPred.indirectMisses 178910 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 99353 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,6 +414,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 68420 # Table walker walks requested system.cpu0.dtb.walker.walksShort 68420 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46092 # Level at which table walker walks with short descriptors terminate @@ -460,6 +467,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 31880381 # DTB hits system.cpu0.dtb.misses 68420 # DTB misses system.cpu0.dtb.accesses 31948801 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -489,6 +497,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3977 # Table walker walks requested system.cpu0.itb.walker.walksShort 3977 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 304 # Level at which table walker walks with short descriptors terminate @@ -542,6 +551,21 @@ system.cpu0.itb.inst_accesses 38610243 # IT system.cpu0.itb.hits 38606266 # DTB hits system.cpu0.itb.misses 3977 # DTB misses system.cpu0.itb.accesses 38610243 # DTB accesses +system.cpu0.numPwrStateTransitions 3704 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1852 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1492233091.644168 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23940880637.068275 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1073 57.94% 57.94% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 772 41.68% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499965331660 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1852 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 83611720275 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2763615685725 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 167224982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -591,6 +615,7 @@ system.cpu0.kern.inst.arm 0 # nu system.cpu0.kern.inst.quiesce 1852 # number of quiesce instructions executed system.cpu0.tickCycles 128530134 # Number of cycles that the object actually ticked system.cpu0.idleCycles 38694848 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 715130 # number of replacements system.cpu0.dcache.tags.tagsinuse 500.249385 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 30394670 # Total number of references to valid blocks. @@ -607,6 +632,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 70 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 63780153 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 63780153 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 15810332 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 15810332 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 13424812 # number of WriteReq hits @@ -783,6 +809,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 224330.935601 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 224330.935601 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115836.194348 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115836.194348 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1962004 # number of replacements system.cpu0.icache.tags.tagsinuse 511.774944 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 36636559 # Total number of references to valid blocks. @@ -799,6 +826,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 101 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 79160710 # Number of tag accesses system.cpu0.icache.tags.data_accesses 79160710 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 36636559 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 36636559 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 36636559 # number of demand (read+write) hits @@ -879,12 +907,14 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92626.848362 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92626.848362 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92626.848362 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841200 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1841258 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 233630 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 298119 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16125.660847 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 4682482 # Total number of references to valid blocks. @@ -920,6 +950,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 89320549 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 89320549 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 82730 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5417 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 88147 # number of ReadReq hits @@ -1233,6 +1264,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42660 system.cpu0.toL2Bus.snoop_filter.tot_snoops 346625 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 340732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5893 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 122459 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 2635557 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 19271 # Transaction distribution @@ -1298,6 +1330,7 @@ system.cpu1.branchPred.indirectLookups 3579063 # Nu system.cpu1.branchPred.indirectHits 3516137 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 62926 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 23615 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1327,6 +1360,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 26974 # Table walker walks requested system.cpu1.dtb.walker.walksShort 26974 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20087 # Level at which table walker walks with short descriptors terminate @@ -1383,6 +1417,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 18177508 # DTB hits system.cpu1.dtb.misses 26974 # DTB misses system.cpu1.dtb.accesses 18204482 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1412,6 +1447,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 2420 # Table walker walks requested system.cpu1.itb.walker.walksShort 2420 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate @@ -1470,6 +1506,21 @@ system.cpu1.itb.inst_accesses 39605220 # IT system.cpu1.itb.hits 39602800 # DTB hits system.cpu1.itb.misses 2420 # DTB misses system.cpu1.itb.accesses 39605220 # DTB accesses +system.cpu1.numPwrStateTransitions 5553 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2777 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1004505001.039251 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25654466824.490025 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1974 71.08% 71.08% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 799 28.77% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 949981296504 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2777 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 57717018114 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2789510387886 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 115435582 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1519,6 +1570,7 @@ system.cpu1.kern.inst.arm 0 # nu system.cpu1.kern.inst.quiesce 2777 # number of quiesce instructions executed system.cpu1.tickCycles 97896037 # Number of cycles that the object actually ticked system.cpu1.idleCycles 17539545 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 196286 # number of replacements system.cpu1.dcache.tags.tagsinuse 471.109798 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 17737294 # Total number of references to valid blocks. @@ -1534,6 +1586,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 63 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 36398755 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 36398755 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 10795076 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 10795076 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 6704752 # number of WriteReq hits @@ -1710,6 +1763,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171920.653078 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171920.653078 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94713.295394 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 94713.295394 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 946364 # number of replacements system.cpu1.icache.tags.tagsinuse 499.210861 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 38654025 # Total number of references to valid blocks. @@ -1725,6 +1779,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 80148678 # Number of tag accesses system.cpu1.icache.tags.data_accesses 80148678 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 38654025 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 38654025 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 38654025 # number of demand (read+write) hits @@ -1805,12 +1860,14 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 93522.321429 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93522.321429 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 93522.321429 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 199879 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 199934 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 48 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 58626 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 53638 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15286.424872 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 2058198 # Total number of references to valid blocks. @@ -1843,6 +1900,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.840820 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 38543839 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 38543839 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 30076 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 3135 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 33211 # number of ReadReq hits @@ -2144,6 +2202,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20164 system.cpu1.toL2Bus.snoop_filter.tot_snoops 192169 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 190372 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1797 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 53056 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 1216172 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 11758 # Transaction distribution @@ -2196,6 +2255,7 @@ system.cpu1.toL2Bus.respLayer2.occupancy 4659998 # La system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 33872477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31003 # Transaction distribution system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2290,6 +2350,7 @@ system.iobus.respLayer0.occupancy 84718000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36449 # number of replacements system.iocache.tags.tagsinuse 14.476064 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2304,6 +2365,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328203 # Number of tag accesses system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2384,6 +2446,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 68759.610031 system.iocache.demand_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68759.610031 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68759.610031 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 131721 # number of replacements system.l2c.tags.tagsinuse 63119.316885 # Cycle average of tags in use system.l2c.tags.total_refs 480965 # Total number of references to valid blocks. @@ -2429,6 +2492,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.001205 # P system.l2c.tags.occ_task_id_percent::1024 0.554291 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 6440622 # Number of tag accesses system.l2c.tags.data_accesses 6440622 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 269250 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 269250 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 33826 # number of UpgradeReq hits @@ -2886,6 +2950,7 @@ system.membus.snoop_filter.hit_multi_requests 567 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 38557 # Transaction distribution system.membus.trans_dist::ReadResp 213679 # Transaction distribution system.membus.trans_dist::WriteReq 31029 # Transaction distribution @@ -2940,12 +3005,21 @@ system.membus.respLayer2.occupancy 1133893717 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1318131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2977,16 +3051,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 1068358 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 578478 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 169754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 19773 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 18732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 1041 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2847227406000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 38560 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 513452 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 31029 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 9c380c00f..ddbc8e898 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.858505 # Nu sim_ticks 2858505242500 # Number of ticks simulated final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125507 # Simulator instruction rate (inst/s) -host_op_rate 151748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3206183180 # Simulator tick rate (ticks/s) -host_mem_usage 578080 # Number of bytes of host memory used -host_seconds 891.56 # Real time elapsed on the host +host_inst_rate 258042 # Simulator instruction rate (inst/s) +host_op_rate 311992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6591883972 # Simulator tick rate (ticks/s) +host_mem_usage 625700 # Number of bytes of host memory used +host_seconds 433.64 # Real time elapsed on the host sim_insts 111897168 # Number of instructions simulated sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory @@ -312,6 +313,7 @@ system.physmem_1.memoryStateTime::REF 95451720000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 512 # Number of instructions bytes read from this memory @@ -324,6 +326,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 179 system.realview.nvmem.bw_inst_read::total 179 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 179 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 179 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -344,6 +349,7 @@ system.cpu.branchPred.indirectHits 2857246 # Nu system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -373,6 +379,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 66151 # Table walker walks requested system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate @@ -422,6 +429,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 44135237 # DTB hits system.cpu.dtb.misses 66151 # DTB misses system.cpu.dtb.accesses 44201388 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,6 +459,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 5761 # Table walker walks requested system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate @@ -500,6 +509,21 @@ system.cpu.itb.inst_accesses 57339683 # IT system.cpu.itb.hits 57333922 # DTB hits system.cpu.itb.misses 5761 # DTB misses system.cpu.itb.accesses 57339683 # DTB accesses +system.cpu.numPwrStateTransitions 6066 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887601126.287174 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17445279478.153702 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2969 97.89% 97.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499966497156 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 166411026471 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2692094216029 # Cumulative time (in ticks) in various power states system.cpu.numCycles 332822103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -549,6 +573,7 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 842468 # number of replacements system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42541759 # Total number of references to valid blocks. @@ -565,6 +590,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 175934555 # Number of tag accesses system.cpu.dcache.tags.data_accesses 175934555 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 23016255 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23016255 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18262413 # number of WriteReq hits @@ -733,6 +759,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106928.531280 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106928.531280 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2894371 # number of replacements system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. @@ -749,6 +776,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 199 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits @@ -829,6 +857,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96490 # number of replacements system.cpu.l2cache.tags.tagsinuse 65016.669962 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7024998 # Total number of references to valid blocks. @@ -858,6 +887,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000824 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 60430282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 60430282 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71969 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4812 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 76781 # number of ReadReq hits @@ -1138,6 +1168,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution @@ -1187,6 +1218,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 11196996 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1281,6 +1313,7 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36424 # number of replacements system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1295,6 +1328,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328122 # Number of tag accesses system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1375,6 +1409,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 75531.049344 system.iocache.demand_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75531.049344 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75531.049344 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34891 # Transaction distribution system.membus.trans_dist::ReadResp 72400 # Transaction distribution system.membus.trans_dist::WriteReq 27583 # Transaction distribution @@ -1428,12 +1463,21 @@ system.membus.respLayer2.occupancy 990225250 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1465,9 +1509,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2858505242500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 6ca509034..208966b9b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104475 # Simulator instruction rate (inst/s) -host_op_rate 126719 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2616817312 # Simulator tick rate (ticks/s) -host_mem_usage 625044 # Number of bytes of host memory used -host_seconds 1082.56 # Real time elapsed on the host +host_inst_rate 118022 # Simulator instruction rate (inst/s) +host_op_rate 143150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2956132692 # Simulator tick rate (ticks/s) +host_mem_usage 626728 # Number of bytes of host memory used +host_seconds 958.30 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory @@ -314,6 +315,7 @@ system.physmem_1.memoryStateTime::REF 94595280000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -326,6 +328,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -346,6 +351,7 @@ system.cpu.branchPred.indirectHits 7767748 # Nu system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -375,6 +381,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 9708 # Table walker walks requested system.cpu.checker.dtb.walker.walksShort 9708 # Table walker walks initiated with short descriptors system.cpu.checker.dtb.walker.walkWaitTime::samples 9708 # Table walker wait (enqueue to first request) latency @@ -414,6 +421,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 44208974 # DTB hits system.cpu.checker.dtb.misses 9708 # DTB misses system.cpu.checker.dtb.accesses 44218682 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -443,6 +451,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency @@ -482,9 +491,11 @@ system.cpu.checker.itb.inst_accesses 115803604 # IT system.cpu.checker.itb.hits 115798779 # DTB hits system.cpu.checker.itb.misses 4825 # DTB misses system.cpu.checker.itb.accesses 115803604 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 139031272 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -514,6 +525,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 72368 # Table walker walks requested system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate @@ -587,6 +599,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 45276053 # DTB hits system.cpu.dtb.misses 72368 # DTB misses system.cpu.dtb.accesses 45348421 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -616,6 +629,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 12817 # Table walker walks requested system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate @@ -687,6 +701,20 @@ system.cpu.itb.inst_accesses 66008446 # IT system.cpu.itb.hits 65995629 # DTB hits system.cpu.itb.misses 12817 # DTB misses system.cpu.itb.accesses 66008446 # DTB accesses +system.cpu.numPwrStateTransitions 6074 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states system.cpu.numCycles 278423951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -981,6 +1009,7 @@ system.cpu.cc_regfile_reads 502156067 # nu system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. @@ -997,6 +1026,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits @@ -1165,6 +1195,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1886245 # number of replacements system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. @@ -1182,6 +1213,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::3 2 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits @@ -1268,6 +1300,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96776 # number of replacements system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. @@ -1297,6 +1330,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits @@ -1579,6 +1613,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution @@ -1628,6 +1663,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 18839481 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30172 # Transaction distribution system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1722,6 +1758,7 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36413 # number of replacements system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1736,6 +1773,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328023 # Number of tag accesses system.iocache.tags.data_accesses 328023 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1816,6 +1854,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34132 # Transaction distribution system.membus.trans_dist::ReadResp 67490 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution @@ -1869,12 +1908,21 @@ system.membus.respLayer2.occupancy 978576250 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1906,10 +1954,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 315f9ca65..6bbe66965 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.825960 # Nu sim_ticks 2825959731500 # Number of ticks simulated final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152939 # Simulator instruction rate (inst/s) -host_op_rate 185526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3598106166 # Simulator tick rate (ticks/s) -host_mem_usage 665816 # Number of bytes of host memory used -host_seconds 785.40 # Real time elapsed on the host +host_inst_rate 153141 # Simulator instruction rate (inst/s) +host_op_rate 185771 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3602870624 # Simulator tick rate (ticks/s) +host_mem_usage 666712 # Number of bytes of host memory used +host_seconds 784.36 # Real time elapsed on the host sim_insts 120118276 # Number of instructions simulated sim_ops 145712235 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory @@ -344,6 +345,7 @@ system.physmem_1.memoryStateTime::REF 94364920000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -362,6 +364,9 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -382,6 +387,7 @@ system.cpu0.branchPred.indirectHits 9964028 # Nu system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -411,6 +417,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 67255 # Table walker walks requested system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate @@ -489,6 +496,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 41220590 # DTB hits system.cpu0.dtb.misses 67255 # DTB misses system.cpu0.dtb.accesses 41287845 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,6 +526,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 10944 # Table walker walks requested system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate @@ -586,6 +595,19 @@ system.cpu0.itb.inst_accesses 72719816 # IT system.cpu0.itb.hits 72708872 # DTB hits system.cpu0.itb.misses 10944 # DTB misses system.cpu0.itb.accesses 72719816 # DTB accesses +system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 202299816 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -880,6 +902,7 @@ system.cpu0.cc_regfile_reads 464897652 # nu system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 709828 # number of replacements system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. @@ -896,6 +919,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits @@ -1072,6 +1096,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1253795 # number of replacements system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. @@ -1088,6 +1113,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits @@ -1174,12 +1200,14 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 276743 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. @@ -1216,6 +1244,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits @@ -1533,6 +1562,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution @@ -1598,6 +1628,7 @@ system.cpu1.branchPred.indirectLookups 249142 # Nu system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1627,6 +1658,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 21410 # Table walker walks requested system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate @@ -1708,6 +1740,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 7689335 # DTB hits system.cpu1.dtb.misses 21410 # DTB misses system.cpu1.dtb.accesses 7710745 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1737,6 +1770,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 5994 # Table walker walks requested system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate @@ -1807,6 +1841,22 @@ system.cpu1.itb.inst_accesses 8259433 # IT system.cpu1.itb.hits 8253439 # DTB hits system.cpu1.itb.misses 5994 # DTB misses system.cpu1.itb.accesses 8259433 # DTB accesses +system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 34887121 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -2101,6 +2151,7 @@ system.cpu1.cc_regfile_reads 75464831 # nu system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 189214 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. @@ -2116,6 +2167,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits @@ -2292,6 +2344,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 585593 # number of replacements system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. @@ -2307,6 +2360,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits @@ -2393,12 +2447,14 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 51951 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. @@ -2431,6 +2487,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 22984 # number of ReadReq hits @@ -2742,6 +2799,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution @@ -2794,6 +2852,7 @@ system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # La system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2888,6 +2947,7 @@ system.iobus.respLayer0.occupancy 84717000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2902,6 +2962,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2982,6 +3043,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 132778 # number of replacements system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. @@ -3029,6 +3091,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.000458 # P system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 6131058 # Number of tag accesses system.l2c.tags.data_accesses 6131058 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits @@ -3513,6 +3576,7 @@ system.membus.snoop_filter.hit_multi_requests 572 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 37951 # Transaction distribution system.membus.trans_dist::ReadResp 212466 # Transaction distribution system.membus.trans_dist::WriteReq 30885 # Transaction distribution @@ -3567,12 +3631,21 @@ system.membus.respLayer2.occupancy 1121401156 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3604,16 +3677,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index d9c520ab2..95f1cb47c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159961 # Simulator instruction rate (inst/s) -host_op_rate 194019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4006592882 # Simulator tick rate (ticks/s) -host_mem_usage 625056 # Number of bytes of host memory used -host_seconds 707.05 # Real time elapsed on the host +host_inst_rate 159277 # Simulator instruction rate (inst/s) +host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3989457396 # Simulator tick rate (ticks/s) +host_mem_usage 626716 # Number of bytes of host memory used +host_seconds 710.09 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory @@ -314,6 +315,7 @@ system.physmem_1.memoryStateTime::REF 94595280000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory @@ -326,6 +328,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 40 system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -346,6 +351,7 @@ system.cpu.branchPred.indirectHits 7767748 # Nu system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -375,6 +381,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 72368 # Table walker walks requested system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate @@ -448,6 +455,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 45276053 # DTB hits system.cpu.dtb.misses 72368 # DTB misses system.cpu.dtb.accesses 45348421 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -477,6 +485,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 12817 # Table walker walks requested system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate @@ -548,6 +557,20 @@ system.cpu.itb.inst_accesses 66008446 # IT system.cpu.itb.hits 65995629 # DTB hits system.cpu.itb.misses 12817 # DTB misses system.cpu.itb.accesses 66008446 # DTB accesses +system.cpu.numPwrStateTransitions 6074 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states system.cpu.numCycles 278423951 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -842,6 +865,7 @@ system.cpu.cc_regfile_reads 502156061 # nu system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. @@ -858,6 +882,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits @@ -1026,6 +1051,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1886245 # number of replacements system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. @@ -1043,6 +1069,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::3 2 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits @@ -1129,6 +1156,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96776 # number of replacements system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. @@ -1158,6 +1186,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits @@ -1440,6 +1469,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution @@ -1489,6 +1519,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 18839481 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30172 # Transaction distribution system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1583,6 +1614,7 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36413 # number of replacements system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1597,6 +1629,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328023 # Number of tag accesses system.iocache.tags.data_accesses 328023 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses system.iocache.ReadReq_misses::total 223 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -1677,6 +1710,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 34132 # Transaction distribution system.membus.trans_dist::ReadResp 67490 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution @@ -1730,12 +1764,21 @@ system.membus.respLayer2.occupancy 978576250 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1767,10 +1810,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 281ec2c99..a15af7782 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.823729 # Nu sim_ticks 2823728611500 # Number of ticks simulated final_tick 2823728611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 406612 # Simulator instruction rate (inst/s) -host_op_rate 493225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9343639540 # Simulator tick rate (ticks/s) -host_mem_usage 632204 # Number of bytes of host memory used -host_seconds 302.21 # Real time elapsed on the host +host_inst_rate 403127 # Simulator instruction rate (inst/s) +host_op_rate 488997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9263554618 # Simulator tick rate (ticks/s) +host_mem_usage 632872 # Number of bytes of host memory used +host_seconds 304.82 # Real time elapsed on the host sim_insts 122881667 # Number of instructions simulated sim_ops 149056790 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 538276 # Number of bytes read from this memory @@ -362,6 +363,7 @@ system.physmem_1.memoryStateTime::REF 91875680000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 17119309500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -374,6 +376,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -381,6 +386,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,6 +416,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 4971 # Table walker walks requested system.cpu0.dtb.walker.walksShort 4971 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walkWaitTime::samples 4971 # Table walker wait (enqueue to first request) latency @@ -451,6 +458,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 21242670 # DTB hits system.cpu0.dtb.misses 4971 # DTB misses system.cpu0.dtb.accesses 21247641 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,6 +488,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 2431 # Table walker walks requested system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency @@ -521,6 +530,21 @@ system.cpu0.itb.inst_accesses 56923097 # IT system.cpu0.itb.hits 56920666 # DTB hits system.cpu0.itb.misses 2431 # DTB misses system.cpu0.itb.accesses 56923097 # DTB accesses +system.cpu0.numPwrStateTransitions 2544 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1272 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2140717570.690252 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 53412982832.831551 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1258 98.90% 98.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10 0.79% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.76% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1799910941001 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1272 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 100735861582 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722992749918 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 68768248 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -583,6 +607,7 @@ system.cpu0.op_class::MemWrite 9581986 14.03% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 68312506 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 833701 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996712 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 45908569 # Total number of references to valid blocks. @@ -605,6 +630,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 193086189 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 193086189 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 11466814 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 3604015 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4048059 # number of ReadReq hits @@ -944,6 +970,7 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.332694 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 120633.235844 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119318.443907 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115384.311080 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1971000 # number of replacements system.cpu0.icache.tags.tagsinuse 511.470268 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 93100004 # Total number of references to valid blocks. @@ -967,6 +994,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 97085384 # Number of tag accesses system.cpu0.icache.tags.data_accesses 97085384 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 56179314 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 17648655 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 9977787 # number of ReadReq hits @@ -1113,6 +1141,7 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12688.700584 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12829.404359 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12937.655406 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12853.021015 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1142,6 +1171,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 2016 # Table walker walks requested system.cpu1.dtb.walker.walksShort 2016 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 564 # Level at which table walker walks with short descriptors terminate @@ -1197,6 +1227,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 6609204 # DTB hits system.cpu1.dtb.misses 2016 # DTB misses system.cpu1.dtb.accesses 6611220 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1226,6 +1257,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1033 # Table walker walks requested system.cpu1.itb.walker.walksShort 1033 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 205 # Level at which table walker walks with short descriptors terminate @@ -1279,6 +1311,18 @@ system.cpu1.itb.inst_accesses 17861460 # IT system.cpu1.itb.hits 17860427 # DTB hits system.cpu1.itb.misses 1033 # DTB misses system.cpu1.itb.accesses 17861460 # DTB accesses +system.cpu1.numPwrStateTransitions 700 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 350 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 887126528.134286 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 11718884453.100866 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 345 98.57% 98.57% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.86% 99.43% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 156797355001 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 350 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2513234326653 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 310494284847 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 143797366 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1354,6 +1398,7 @@ system.cpu2.branchPred.indirectLookups 671898 # Nu system.cpu2.branchPred.indirectHits 638941 # Number of indirect target hits. system.cpu2.branchPred.indirectMisses 32957 # Number of indirect misses. system.cpu2.branchPredindirectMispredicted 21982 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1383,6 +1428,7 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu2.dtb.walker.walks 11822 # Table walker walks requested system.cpu2.dtb.walker.walksShort 11822 # Table walker walks initiated with short descriptors system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7337 # Level at which table walker walks with short descriptors terminate @@ -1434,6 +1480,7 @@ system.cpu2.dtb.inst_accesses 0 # IT system.cpu2.dtb.hits 7691653 # DTB hits system.cpu2.dtb.misses 11822 # DTB misses system.cpu2.dtb.accesses 7703475 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1463,6 +1510,7 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu2.itb.walker.walks 1331 # Table walker walks requested system.cpu2.itb.walker.walksShort 1331 # Table walker walks initiated with short descriptors system.cpu2.itb.walker.walksShortTerminationLevel::Level1 253 # Level at which table walker walks with short descriptors terminate @@ -1515,6 +1563,23 @@ system.cpu2.itb.inst_accesses 10454317 # IT system.cpu2.itb.hits 10452986 # DTB hits system.cpu2.itb.misses 1331 # DTB misses system.cpu2.itb.accesses 10454317 # DTB accesses +system.cpu2.numPwrStateTransitions 1086 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 543 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 5039016894.569060 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 41056292942.981247 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 498 91.71% 91.71% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.00% 98.71% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.18% 98.90% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.18% 99.08% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.18% 99.26% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.18% 99.45% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.82% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.18% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 500052575501 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 543 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 87542437749 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736186173751 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 141973763 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1577,6 +1642,7 @@ system.cpu3.branchPred.indirectLookups 2014355 # Nu system.cpu3.branchPred.indirectHits 1952666 # Number of indirect target hits. system.cpu3.branchPred.indirectMisses 61689 # Number of indirect misses. system.cpu3.branchPredindirectMispredicted 18072 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1606,6 +1672,7 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu3.dtb.walker.walks 34281 # Table walker walks requested system.cpu3.dtb.walker.walksShort 34281 # Table walker walks initiated with short descriptors system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10962 # Level at which table walker walks with short descriptors terminate @@ -1689,6 +1756,7 @@ system.cpu3.dtb.inst_accesses 0 # IT system.cpu3.dtb.hits 13165199 # DTB hits system.cpu3.dtb.misses 34281 # DTB misses system.cpu3.dtb.accesses 13199480 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,6 +1786,7 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.cpu3.itb.walker.walks 4255 # Table walker walks requested system.cpu3.itb.walker.walksShort 4255 # Table walker walks initiated with short descriptors system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1348 # Level at which table walker walks with short descriptors terminate @@ -1794,6 +1863,17 @@ system.cpu3.itb.inst_accesses 9885382 # IT system.cpu3.itb.hits 9881127 # DTB hits system.cpu3.itb.misses 4255 # DTB misses system.cpu3.itb.accesses 9885382 # DTB accesses +system.cpu3.numPwrStateTransitions 1752 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 876 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 24094343.119863 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 642903034.341614 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 861 98.29% 98.29% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.71% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::max_value 18909601804 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 876 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 2802621966927 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 21106644573 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 55785273 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -2093,6 +2173,7 @@ system.cpu3.cc_regfile_reads 144202792 # nu system.cpu3.cc_regfile_writes 15932581 # number of cc regfile writes system.cpu3.misc_regfile_reads 98044086 # number of misc regfile reads system.cpu3.misc_regfile_writes 343753 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2171,6 +2252,7 @@ system.iobus.respLayer0.occupancy 50308000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36410 # number of replacements system.iocache.tags.tagsinuse 1.002475 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2185,6 +2267,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 327996 # Number of tag accesses system.iocache.tags.data_accesses 327996 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses system.iocache.ReadReq_misses::total 220 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2265,6 +2348,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 70054.816134 system.iocache.demand_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 70054.816134 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70054.816134 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 100820 # number of replacements system.l2c.tags.tagsinuse 65104.875407 # Cycle average of tags in use system.l2c.tags.total_refs 5136845 # Total number of references to valid blocks. @@ -2316,6 +2400,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.000900 # P system.l2c.tags.occ_task_id_percent::1024 0.993515 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 45392022 # Number of tag accesses system.l2c.tags.data_accesses 45392022 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 4238 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2128 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 1538 # number of ReadReq hits @@ -2928,6 +3013,7 @@ system.membus.snoop_filter.hit_multi_requests 473 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40114 # Transaction distribution system.membus.trans_dist::ReadResp 75609 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution @@ -2980,12 +3066,21 @@ system.membus.respLayer2.occupancy 649041000 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 721087 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3017,16 +3112,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 5640723 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 2834949 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 44718 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823728611500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 110707 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2619793 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 4bf027a0a..a6bd06312 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.804583 # Nu sim_ticks 2804582834000 # Number of ticks simulated final_tick 2804582834000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167374 # Simulator instruction rate (inst/s) -host_op_rate 203147 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4015325540 # Simulator tick rate (ticks/s) -host_mem_usage 633236 # Number of bytes of host memory used -host_seconds 698.47 # Real time elapsed on the host +host_inst_rate 172391 # Simulator instruction rate (inst/s) +host_op_rate 209235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4135673798 # Simulator tick rate (ticks/s) +host_mem_usage 633896 # Number of bytes of host memory used +host_seconds 678.14 # Real time elapsed on the host sim_insts 116905819 # Number of instructions simulated sim_ops 141891765 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 3968 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 685504 # Number of bytes read from this memory @@ -335,6 +336,7 @@ system.physmem_1.memoryStateTime::REF 93650960000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 24067808750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory @@ -347,6 +349,9 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 274 system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -367,6 +372,7 @@ system.cpu0.branchPred.indirectHits 4401835 # Nu system.cpu0.branchPred.indirectMisses 111638 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 31883 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,6 +402,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 59132 # Table walker walks requested system.cpu0.dtb.walker.walksShort 59132 # Table walker walks initiated with short descriptors system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17796 # Level at which table walker walks with short descriptors terminate @@ -478,6 +485,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 24015751 # DTB hits system.cpu0.dtb.misses 59132 # DTB misses system.cpu0.dtb.accesses 24074883 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,6 +515,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 7852 # Table walker walks requested system.cpu0.itb.walker.walksShort 7852 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2338 # Level at which table walker walks with short descriptors terminate @@ -581,6 +590,19 @@ system.cpu0.itb.inst_accesses 19913313 # IT system.cpu0.itb.hits 19905461 # DTB hits system.cpu0.itb.misses 7852 # DTB misses system.cpu0.itb.accesses 19913313 # DTB accesses +system.cpu0.numPwrStateTransitions 3146 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1573 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 939647394.777495 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 18797497095.969948 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1537 97.71% 97.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499976908600 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1573 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1326517482015 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478065351985 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 106457732 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -880,6 +902,7 @@ system.cpu0.cc_regfile_reads 262463335 # nu system.cpu0.cc_regfile_writes 27226302 # number of cc regfile writes system.cpu0.misc_regfile_reads 188101438 # number of misc regfile reads system.cpu0.misc_regfile_writes 725062 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 852281 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.984445 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 42339308 # Total number of references to valid blocks. @@ -898,6 +921,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 189174355 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 189174355 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 12233622 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 12935174 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 25168796 # number of ReadReq hits @@ -1146,6 +1170,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202532.431651 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102368.142579 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113511.329191 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107377.271721 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 1934770 # number of replacements system.cpu0.icache.tags.tagsinuse 511.556955 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 38706180 # Total number of references to valid blocks. @@ -1165,6 +1190,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 42724671 # Number of tag accesses system.cpu0.icache.tags.data_accesses 42724671 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 18869611 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 19836569 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 38706180 # number of ReadReq hits @@ -1297,6 +1323,7 @@ system.cpu1.branchPred.indirectLookups 4615749 # Nu system.cpu1.branchPred.indirectHits 4505317 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 110432 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 32773 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1326,6 +1353,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 58704 # Table walker walks requested system.cpu1.dtb.walker.walksShort 58704 # Table walker walks initiated with short descriptors system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18787 # Level at which table walker walks with short descriptors terminate @@ -1411,6 +1439,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 25209314 # DTB hits system.cpu1.dtb.misses 58704 # DTB misses system.cpu1.dtb.accesses 25268018 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1440,6 +1469,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 7547 # Table walker walks requested system.cpu1.itb.walker.walksShort 7547 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2262 # Level at which table walker walks with short descriptors terminate @@ -1513,6 +1543,20 @@ system.cpu1.itb.inst_accesses 20896420 # IT system.cpu1.itb.hits 20888873 # DTB hits system.cpu1.itb.misses 7547 # DTB misses system.cpu1.itb.accesses 20896420 # DTB accesses +system.cpu1.numPwrStateTransitions 2930 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 1465 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 831651178.963822 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 15817593716.503048 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1430 97.61% 97.61% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 32 2.18% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 499953823748 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 1465 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1586213856818 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218368977182 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 109807766 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1812,6 +1856,7 @@ system.cpu1.cc_regfile_reads 280643076 # nu system.cpu1.cc_regfile_writes 29716175 # number of cc regfile writes system.cpu1.misc_regfile_reads 196047925 # number of misc regfile reads system.cpu1.misc_regfile_writes 794523 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1906,6 +1951,7 @@ system.iobus.respLayer0.occupancy 82688000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36409 # number of replacements system.iocache.tags.tagsinuse 0.981814 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. @@ -1920,6 +1966,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328227 # Number of tag accesses system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits @@ -2006,6 +2053,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 68271.921222 system.iocache.demand_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68271.921222 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68271.921222 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 104354 # number of replacements system.l2c.tags.tagsinuse 65128.327411 # Cycle average of tags in use system.l2c.tags.total_refs 5134678 # Total number of references to valid blocks. @@ -2041,6 +2089,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.001190 # P system.l2c.tags.occ_task_id_percent::1024 0.994522 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 45398834 # Number of tag accesses system.l2c.tags.data_accesses 45398834 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 35730 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 6852 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 36375 # number of ReadReq hits @@ -2462,6 +2511,7 @@ system.membus.snoop_filter.hit_multi_requests 505 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 31794 # Transaction distribution system.membus.trans_dist::ReadResp 68215 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution @@ -2515,12 +2565,21 @@ system.membus.respLayer2.occupancy 1008874750 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 1321623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2552,16 +2611,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 5615551 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 2827345 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 47668 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 189 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804582834000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 149135 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2640787 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index 3e87001d4..e65448f88 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 47.355903 # Nu sim_ticks 47355903328000 # Number of ticks simulated final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234942 # Simulator instruction rate (inst/s) -host_op_rate 276333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12593783431 # Simulator tick rate (ticks/s) -host_mem_usage 765460 # Number of bytes of host memory used -host_seconds 3760.26 # Real time elapsed on the host +host_inst_rate 277163 # Simulator instruction rate (inst/s) +host_op_rate 325991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14856975599 # Simulator tick rate (ticks/s) +host_mem_usage 813232 # Number of bytes of host memory used +host_seconds 3187.45 # Real time elapsed on the host sim_insts 883443630 # Number of instructions simulated sim_ops 1039082168 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory @@ -357,6 +358,7 @@ system.physmem_1.memoryStateTime::REF 1581317660000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory @@ -383,6 +385,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -403,6 +408,7 @@ system.cpu0.branchPred.indirectHits 2658726 # Nu system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -432,6 +438,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 298304 # Table walker walks requested system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate @@ -487,6 +494,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176008306 # DTB hits system.cpu0.dtb.misses 298304 # DTB misses system.cpu0.dtb.accesses 176306610 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,6 +524,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 65048 # Table walker walks requested system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate @@ -576,6 +585,24 @@ system.cpu0.itb.inst_accesses 259268632 # IT system.cpu0.itb.hits 259203584 # DTB hits system.cpu0.itb.misses 65048 # DTB misses system.cpu0.itb.accesses 259268632 # DTB accesses +system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 1023758481 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -625,6 +652,7 @@ system.cpu0.kern.inst.arm 0 # nu system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 6026209 # number of replacements system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. @@ -642,6 +670,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits @@ -842,6 +871,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 9817579 # number of replacements system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. @@ -858,6 +888,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits @@ -938,12 +969,14 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 2829183 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. @@ -979,6 +1012,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits @@ -1318,6 +1352,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution @@ -1386,6 +1421,7 @@ system.cpu1.branchPred.indirectLookups 3290763 # Nu system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1415,6 +1451,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 255224 # Table walker walks requested system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate @@ -1470,6 +1507,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 148139102 # DTB hits system.cpu1.dtb.misses 255224 # DTB misses system.cpu1.dtb.accesses 148394326 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1499,6 +1537,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 62177 # Table walker walks requested system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate @@ -1559,6 +1598,24 @@ system.cpu1.itb.inst_accesses 219399751 # IT system.cpu1.itb.hits 219337574 # DTB hits system.cpu1.itb.misses 62177 # DTB misses system.cpu1.itb.accesses 219399751 # DTB accesses +system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 838096745 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1608,6 +1665,7 @@ system.cpu1.kern.inst.arm 0 # nu system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 4810857 # number of replacements system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. @@ -1624,6 +1682,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits @@ -1824,6 +1883,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 8744967 # number of replacements system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. @@ -1840,6 +1900,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits @@ -1920,12 +1981,14 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 2218428 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. @@ -1961,6 +2024,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits @@ -2317,6 +2381,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution @@ -2371,6 +2436,7 @@ system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # La system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40337 # Transaction distribution system.iobus.trans_dist::ReadResp 40337 # Transaction distribution system.iobus.trans_dist::WriteReq 136616 # Transaction distribution @@ -2447,6 +2513,7 @@ system.iobus.respLayer3.occupancy 147924000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115611 # number of replacements system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -2463,6 +2530,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040883 # Number of tag accesses system.iocache.tags.data_accesses 1040883 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses @@ -2588,6 +2656,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1371243 # number of replacements system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. @@ -2636,6 +2705,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.003891 # P system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 79235647 # Number of tag accesses system.l2c.tags.data_accesses 79235647 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -3160,6 +3230,7 @@ system.membus.snoop_filter.hit_multi_requests 2908 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 91033 # Transaction distribution system.membus.trans_dist::ReadResp 892432 # Transaction distribution system.membus.trans_dist::WriteReq 38505 # Transaction distribution @@ -3214,12 +3285,21 @@ system.membus.respLayer2.occupancy 5231778477 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3262,16 +3342,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 9c49f3e4a..1618cff36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.660653 # Nu sim_ticks 51660652947000 # Number of ticks simulated final_tick 51660652947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260799 # Simulator instruction rate (inst/s) -host_op_rate 306450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14496494193 # Simulator tick rate (ticks/s) -host_mem_usage 677256 # Number of bytes of host memory used -host_seconds 3563.67 # Real time elapsed on the host +host_inst_rate 288085 # Simulator instruction rate (inst/s) +host_op_rate 338513 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16013200726 # Simulator tick rate (ticks/s) +host_mem_usage 724944 # Number of bytes of host memory used +host_seconds 3226.13 # Real time elapsed on the host sim_insts 929398934 # Number of instructions simulated sim_ops 1092086880 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 378560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 313536 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 10229888 # Number of bytes read from this memory @@ -320,6 +321,7 @@ system.physmem_1.memoryStateTime::REF 1725062560000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 292938700991 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory @@ -336,6 +338,9 @@ system.realview.nvmem.bw_inst_read::total 14 # I system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -356,6 +361,7 @@ system.cpu.branchPred.indirectHits 5016643 # Nu system.cpu.branchPred.indirectMisses 2055396 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 841768 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 561578 # Table walker walks requested system.cpu.dtb.walker.walksLong 561578 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20867 # Level at which table walker walks with long descriptors terminate @@ -442,6 +449,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 338792432 # DTB hits system.cpu.dtb.misses 561578 # DTB misses system.cpu.dtb.accesses 339354010 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -471,6 +479,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 133823 # Table walker walks requested system.cpu.itb.walker.walksLong 133823 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1057 # Level at which table walker walks with long descriptors terminate @@ -526,6 +535,27 @@ system.cpu.itb.inst_accesses 442926878 # IT system.cpu.itb.hits 442793055 # DTB hits system.cpu.itb.misses 133823 # DTB misses system.cpu.itb.accesses 442926878 # DTB accesses +system.cpu.numPwrStateTransitions 33032 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16516 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3050356912.427888 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59773934276.156128 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7219 43.71% 43.71% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9262 56.08% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988777743356 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16516 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1280958181341 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50379694765659 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2561963341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -575,6 +605,7 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 16516 # number of quiesce instructions executed system.cpu.tickCycles 1757425284 # Number of cycles that the object actually ticked system.cpu.idleCycles 804538057 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 10826762 # number of replacements system.cpu.dcache.tags.tagsinuse 511.930071 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 322795140 # Total number of references to valid blocks. @@ -592,6 +623,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1356106386 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1356106386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 165131668 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 165131668 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148654336 # number of WriteReq hits @@ -782,6 +814,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183922.263109 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183922.263109 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91948.852425 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91948.852425 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24339101 # number of replacements system.cpu.icache.tags.tagsinuse 511.885333 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418129059 # Total number of references to valid blocks. @@ -798,6 +831,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 108 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 466808304 # Number of tag accesses system.cpu.icache.tags.data_accesses 466808304 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 418129059 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 418129059 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 418129059 # number of demand (read+write) hits @@ -878,6 +912,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1529682 # number of replacements system.cpu.l2cache.tags.tagsinuse 65330.827855 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 66339690 # Total number of references to valid blocks. @@ -908,6 +943,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003632 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958176 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 577322417 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 577322417 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 919591 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 277608 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1197199 # number of ReadReq hits @@ -1212,6 +1248,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4125 system.cpu.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1731601 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 33371848 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution @@ -1262,6 +1299,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 400149367 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 1245546930 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40324 # Transaction distribution system.iobus.trans_dist::ReadResp 40324 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1338,6 +1376,7 @@ system.iobus.respLayer3.occupancy 147766000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115484 # number of replacements system.iocache.tags.tagsinuse 10.441254 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1354,6 +1393,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039884 # Number of tag accesses system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses @@ -1479,6 +1519,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 80309.018824 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80307.212471 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80309.018824 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 86006 # Transaction distribution system.membus.trans_dist::ReadResp 535040 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution @@ -1532,12 +1573,21 @@ system.membus.respLayer2.occupancy 6128850630 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44857615 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1580,9 +1630,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51660652947000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 5d9de1414..c78c1552c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134762 # Simulator instruction rate (inst/s) -host_op_rate 158348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8155197699 # Simulator tick rate (ticks/s) -host_mem_usage 681612 # Number of bytes of host memory used -host_seconds 6293.79 # Real time elapsed on the host +host_inst_rate 139208 # Simulator instruction rate (inst/s) +host_op_rate 163572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8424230073 # Simulator tick rate (ticks/s) +host_mem_usage 729304 # Number of bytes of host memory used +host_seconds 6092.80 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory @@ -323,6 +324,7 @@ system.physmem_1.memoryStateTime::REF 1713925980000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -339,6 +341,9 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -359,6 +364,7 @@ system.cpu.branchPred.indirectHits 4744517 # Nu system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,6 +394,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 197728 # Table walker walks requested system.cpu.checker.dtb.walker.walksLong 197728 # Table walker walks initiated with long descriptors system.cpu.checker.dtb.walker.walkWaitTime::samples 197728 # Table walker wait (enqueue to first request) latency @@ -427,6 +434,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 304308457 # DTB hits system.cpu.checker.dtb.misses 197728 # DTB misses system.cpu.checker.dtb.accesses 304506185 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -456,6 +464,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 119805 # Table walker walks requested system.cpu.checker.itb.walker.walksLong 119805 # Table walker walks initiated with long descriptors system.cpu.checker.itb.walker.walkWaitTime::samples 119805 # Table walker wait (enqueue to first request) latency @@ -495,9 +504,11 @@ system.cpu.checker.itb.inst_accesses 848690490 # IT system.cpu.checker.itb.hits 848570685 # DTB hits system.cpu.checker.itb.misses 119805 # DTB misses system.cpu.checker.itb.accesses 848690490 # DTB accesses +system.cpu.checker.pwrStateResidencyTicks::ON 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 997179501 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -527,6 +538,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 947007 # Table walker walks requested system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate @@ -608,6 +620,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 316731789 # DTB hits system.cpu.dtb.misses 947007 # DTB misses system.cpu.dtb.accesses 317678796 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -637,6 +650,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 162102 # Table walker walks requested system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate @@ -715,6 +729,26 @@ system.cpu.itb.inst_accesses 357169890 # IT system.cpu.itb.hits 357007788 # DTB hits system.cpu.itb.misses 162102 # DTB misses system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.numPwrStateTransitions 32228 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1631144067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1010,6 +1044,7 @@ system.cpu.cc_regfile_reads 225040074 # nu system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9706309 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. @@ -1026,6 +1061,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits @@ -1216,6 +1252,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 15141033 # number of replacements system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. @@ -1232,6 +1269,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 81 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits @@ -1318,6 +1356,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1146896 # number of replacements system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks. @@ -1348,6 +1387,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits @@ -1654,6 +1694,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution @@ -1704,6 +1745,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 426213261 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40299 # Transaction distribution system.iobus.trans_dist::ReadResp 40299 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1780,6 +1822,7 @@ system.iobus.respLayer3.occupancy 147716000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1796,6 +1839,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039659 # Number of tag accesses system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses @@ -1921,6 +1965,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54972 # Transaction distribution system.membus.trans_dist::ReadResp 410008 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution @@ -1974,12 +2019,21 @@ system.membus.respLayer2.occupancy 4069623687 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2022,10 +2076,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index c46aa316c..10b007358 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 47.384315 # Nu sim_ticks 47384315163000 # Number of ticks simulated final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172390 # Simulator instruction rate (inst/s) -host_op_rate 202727 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9043218476 # Simulator tick rate (ticks/s) -host_mem_usage 765852 # Number of bytes of host memory used -host_seconds 5239.76 # Real time elapsed on the host +host_inst_rate 162093 # Simulator instruction rate (inst/s) +host_op_rate 190619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8503081814 # Simulator tick rate (ticks/s) +host_mem_usage 814268 # Number of bytes of host memory used +host_seconds 5572.60 # Real time elapsed on the host sim_insts 903281747 # Number of instructions simulated sim_ops 1062243320 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory @@ -318,6 +319,7 @@ system.physmem_1.memoryStateTime::REF 1582266400000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory @@ -344,6 +346,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -364,6 +369,7 @@ system.cpu0.branchPred.indirectHits 2747803 # Nu system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,6 +399,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 530338 # Table walker walks requested system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate @@ -475,6 +482,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 182736783 # DTB hits system.cpu0.dtb.misses 530338 # DTB misses system.cpu0.dtb.accesses 183267121 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -504,6 +512,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 81834 # Table walker walks requested system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate @@ -584,6 +593,26 @@ system.cpu0.itb.inst_accesses 216603307 # IT system.cpu0.itb.hits 216521473 # DTB hits system.cpu0.itb.misses 81834 # DTB misses system.cpu0.itb.accesses 216603307 # DTB accesses +system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 746014900 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -879,6 +908,7 @@ system.cpu0.cc_regfile_reads 127998327 # nu system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 5793916 # number of replacements system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. @@ -895,6 +925,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits @@ -1093,6 +1124,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 6136519 # number of replacements system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. @@ -1109,6 +1141,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits @@ -1195,12 +1228,14 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 2565485 # number of replacements system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. @@ -1238,6 +1273,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits @@ -1596,6 +1632,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution @@ -1663,6 +1700,7 @@ system.cpu1.branchPred.indirectLookups 4036084 # Nu system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1692,6 +1730,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 579824 # Table walker walks requested system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate @@ -1769,6 +1808,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 169832161 # DTB hits system.cpu1.dtb.misses 579824 # DTB misses system.cpu1.dtb.accesses 170411985 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1798,6 +1838,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 86146 # Table walker walks requested system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate @@ -1875,6 +1916,24 @@ system.cpu1.itb.inst_accesses 200266108 # IT system.cpu1.itb.hits 200179962 # DTB hits system.cpu1.itb.misses 86146 # DTB misses system.cpu1.itb.accesses 200266108 # DTB accesses +system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 683375860 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -2170,6 +2229,7 @@ system.cpu1.cc_regfile_reads 115255782 # nu system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 5420466 # number of replacements system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. @@ -2186,6 +2246,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits @@ -2384,6 +2445,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 5742782 # number of replacements system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. @@ -2400,6 +2462,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits @@ -2486,12 +2549,14 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 2216875 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. @@ -2529,6 +2594,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits @@ -2883,6 +2949,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution @@ -2938,6 +3005,7 @@ system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # La system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40341 # Transaction distribution system.iobus.trans_dist::ReadResp 40341 # Transaction distribution system.iobus.trans_dist::WriteReq 136646 # Transaction distribution @@ -3014,6 +3082,7 @@ system.iobus.respLayer3.occupancy 147918000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115592 # number of replacements system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -3030,6 +3099,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040856 # Number of tag accesses system.iocache.tags.data_accesses 1040856 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses @@ -3155,6 +3225,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1423185 # number of replacements system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. @@ -3204,6 +3275,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.003387 # P system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 76659871 # Number of tag accesses system.l2c.tags.data_accesses 76659871 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits @@ -3724,6 +3796,7 @@ system.membus.snoop_filter.hit_multi_requests 2931 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 60003 # Transaction distribution system.membus.trans_dist::ReadResp 904829 # Transaction distribution system.membus.trans_dist::WriteReq 38534 # Transaction distribution @@ -3778,12 +3851,21 @@ system.membus.respLayer2.occupancy 5223815230 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3826,16 +3908,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 3e88f4b72..7f31e0119 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.327140 # Nu sim_ticks 51327139864000 # Number of ticks simulated final_tick 51327139864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181298 # Simulator instruction rate (inst/s) -host_op_rate 213029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10971364807 # Simulator tick rate (ticks/s) -host_mem_usage 680328 # Number of bytes of host memory used -host_seconds 4678.28 # Real time elapsed on the host +host_inst_rate 184861 # Simulator instruction rate (inst/s) +host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11186950873 # Simulator tick rate (ticks/s) +host_mem_usage 729056 # Number of bytes of host memory used +host_seconds 4588.13 # Real time elapsed on the host sim_insts 848164321 # Number of instructions simulated sim_ops 996610207 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 227712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 216512 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5661728 # Number of bytes read from this memory @@ -323,6 +324,7 @@ system.physmem_1.memoryStateTime::REF 1713925980000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 183585648673 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory @@ -339,6 +341,9 @@ system.realview.nvmem.bw_inst_read::total 7 # I system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -359,6 +364,7 @@ system.cpu.branchPred.indirectHits 4744517 # Nu system.cpu.branchPred.indirectMisses 1985028 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 766036 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,6 +394,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 947007 # Table walker walks requested system.cpu.dtb.walker.walksLong 947007 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15816 # Level at which table walker walks with long descriptors terminate @@ -469,6 +476,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 316731789 # DTB hits system.cpu.dtb.misses 947007 # DTB misses system.cpu.dtb.accesses 317678796 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,6 +506,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 162102 # Table walker walks requested system.cpu.itb.walker.walksLong 162102 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1483 # Level at which table walker walks with long descriptors terminate @@ -576,6 +585,26 @@ system.cpu.itb.inst_accesses 357169890 # IT system.cpu.itb.hits 357007788 # DTB hits system.cpu.itb.misses 162102 # DTB misses system.cpu.itb.accesses 357169890 # DTB accesses +system.cpu.numPwrStateTransitions 32228 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16114 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3134638980.534008 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60494100077.253059 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6793 42.16% 42.16% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9285 57.62% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16114 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 815567331675 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50511572532325 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1631144067 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -871,6 +900,7 @@ system.cpu.cc_regfile_reads 225040074 # nu system.cpu.cc_regfile_writes 225673032 # number of cc regfile writes system.cpu.misc_regfile_reads 2558050117 # number of misc regfile reads system.cpu.misc_regfile_writes 26930699 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9706309 # number of replacements system.cpu.dcache.tags.tagsinuse 511.972800 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 283158526 # Total number of references to valid blocks. @@ -887,6 +917,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1236907465 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1236907465 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147182281 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147182281 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128244124 # number of WriteReq hits @@ -1077,6 +1108,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183859.552230 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183859.552230 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91905.215662 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91905.215662 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 15141033 # number of replacements system.cpu.icache.tags.tagsinuse 511.928986 # Cycle average of tags in use system.cpu.icache.tags.total_refs 340718799 # Total number of references to valid blocks. @@ -1093,6 +1125,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 81 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 371754919 # Number of tag accesses system.cpu.icache.tags.data_accesses 371754919 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 340718799 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 340718799 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 340718799 # number of demand (read+write) hits @@ -1179,6 +1212,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.968724 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.968724 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.968724 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1146896 # number of replacements system.cpu.l2cache.tags.tagsinuse 65342.232394 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 46291207 # Total number of references to valid blocks. @@ -1209,6 +1243,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004486 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946854 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 410454205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 410454205 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 776137 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 292808 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1068945 # number of ReadReq hits @@ -1515,6 +1550,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3563 system.cpu.toL2Bus.snoop_filter.tot_snoops 2189 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2189 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1620273 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23279411 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution @@ -1565,6 +1601,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 426213261 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 1139764793 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40299 # Transaction distribution system.iobus.trans_dist::ReadResp 40299 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1641,6 +1678,7 @@ system.iobus.respLayer3.occupancy 147716000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.423130 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1657,6 +1695,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039659 # Number of tag accesses system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses @@ -1782,6 +1821,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 80670.558242 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85575 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80668.859410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80670.558242 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54972 # Transaction distribution system.membus.trans_dist::ReadResp 410008 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution @@ -1835,12 +1875,21 @@ system.membus.respLayer2.occupancy 4069623687 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44815639 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1883,10 +1932,29 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51327139864000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16114 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index ce7451dc8..037f2a987 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1222140 # Simulator instruction rate (inst/s) -host_op_rate 1436279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63596815146 # Simulator tick rate (ticks/s) -host_mem_usage 673192 # Number of bytes of host memory used -host_seconds 803.68 # Real time elapsed on the host +host_inst_rate 1565564 # Simulator instruction rate (inst/s) +host_op_rate 1839875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81467630636 # Simulator tick rate (ticks/s) +host_mem_usage 722252 # Number of bytes of host memory used +host_seconds 627.38 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory @@ -51,6 +52,7 @@ system.physmem.bw_total::cpu.inst 107295 # To system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -67,6 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -74,6 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -103,6 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 266586 # Table walker walks requested system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency @@ -142,6 +149,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 351319901 # DTB hits system.cpu.dtb.misses 266586 # DTB misses system.cpu.dtb.accesses 351586487 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,6 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -210,6 +219,26 @@ system.cpu.itb.inst_accesses 982807118 # IT system.cpu.itb.hits 982680284 # DTB hits system.cpu.itb.misses 126834 # DTB misses system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.numPwrStateTransitions 33550 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states system.cpu.numCycles 102222351209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -272,6 +301,7 @@ system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1154935820 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 11606642 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. @@ -288,6 +318,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits @@ -360,6 +391,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks system.cpu.dcache.writebacks::total 8917390 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 14265253 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. @@ -376,6 +408,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 89 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits @@ -408,6 +441,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks system.cpu.icache.writebacks::total 14265253 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1725806 # number of replacements system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. @@ -437,6 +471,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits @@ -557,6 +592,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution @@ -595,6 +631,7 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -637,6 +674,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -653,6 +691,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -700,6 +739,7 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution system.membus.trans_dist::ReadResp 524946 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution @@ -742,12 +782,21 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3924997 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -790,9 +839,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 9aa72b24a..3835eafd1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 47.216815 # Nu sim_ticks 47216814802000 # Number of ticks simulated final_tick 47216814802000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1112312 # Simulator instruction rate (inst/s) -host_op_rate 1308465 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53753255119 # Simulator tick rate (ticks/s) -host_mem_usage 687512 # Number of bytes of host memory used -host_seconds 878.40 # Real time elapsed on the host +host_inst_rate 1563637 # Simulator instruction rate (inst/s) +host_op_rate 1839381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75563871924 # Simulator tick rate (ticks/s) +host_mem_usage 737620 # Number of bytes of host memory used +host_seconds 624.86 # Real time elapsed on the host sim_insts 977053655 # Number of instructions simulated sim_ops 1149354696 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 150336 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 124416 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 3895860 # Number of bytes read from this memory @@ -72,6 +73,7 @@ system.physmem.bw_total::cpu1.inst 56510 # To system.physmem.bw_total::cpu1.data 820165 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8847 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3870913 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -98,6 +100,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -105,6 +110,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -134,6 +140,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 124420 # Table walker walks requested system.cpu0.dtb.walker.walksLong 124420 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walkWaitTime::samples 124420 # Table walker wait (enqueue to first request) latency @@ -173,6 +180,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176801329 # DTB hits system.cpu0.dtb.misses 124420 # DTB misses system.cpu0.dtb.accesses 176925749 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,6 +210,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 60852 # Table walker walks requested system.cpu0.itb.walker.walksLong 60852 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walkWaitTime::samples 60852 # Table walker wait (enqueue to first request) latency @@ -241,6 +250,25 @@ system.cpu0.itb.inst_accesses 493698845 # IT system.cpu0.itb.hits 493637993 # DTB hits system.cpu0.itb.misses 60852 # DTB misses system.cpu0.itb.accesses 493698845 # DTB accesses +system.cpu0.numPwrStateTransitions 26456 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13226 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3548051502.510434 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 89670925641.729767 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3168 23.95% 23.95% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10031 75.84% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7470356053852 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13226 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 290285629797 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46926529172203 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 94433642835 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -303,6 +331,7 @@ system.cpu0.op_class::MemWrite 85027076 14.65% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 580566843 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 6218107 # number of replacements system.cpu0.dcache.tags.tagsinuse 503.352532 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 170512705 # Total number of references to valid blocks. @@ -319,6 +348,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 359988587 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 359988587 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 85387960 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 85387960 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 80242803 # number of WriteReq hits @@ -391,6 +421,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 6218107 # number of writebacks system.cpu0.dcache.writebacks::total 6218107 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 5488502 # number of replacements system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 488204417 # Total number of references to valid blocks. @@ -408,6 +439,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 992875891 # Number of tag accesses system.cpu0.icache.tags.data_accesses 992875891 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 488204417 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 488204417 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 488204417 # number of demand (read+write) hits @@ -440,12 +472,14 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.writebacks::writebacks 5488502 # number of writebacks system.cpu0.icache.writebacks::total 5488502 # number of writebacks +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 2643580 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16147.870386 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 15444293 # Total number of references to valid blocks. @@ -473,6 +507,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973450 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 394033422 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 394033422 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 293436 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 155846 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 449282 # number of ReadReq hits @@ -593,6 +628,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1374 system.cpu0.toL2Bus.snoop_filter.tot_snoops 1770017 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1769681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 336 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 619965 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 10275461 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 33238 # Transaction distribution @@ -630,6 +666,7 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 30354370 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -659,6 +696,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 144355 # Table walker walks requested system.cpu1.dtb.walker.walksLong 144355 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walkWaitTime::samples 144355 # Table walker wait (enqueue to first request) latency @@ -698,6 +736,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 173467628 # DTB hits system.cpu1.dtb.misses 144355 # DTB misses system.cpu1.dtb.accesses 173611983 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -727,6 +766,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 61638 # Table walker walks requested system.cpu1.itb.walker.walksLong 61638 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walkWaitTime::samples 61638 # Table walker wait (enqueue to first request) latency @@ -766,6 +806,23 @@ system.cpu1.itb.inst_accesses 483964018 # IT system.cpu1.itb.hits 483902380 # DTB hits system.cpu1.itb.misses 61638 # DTB misses system.cpu1.itb.accesses 483964018 # DTB accesses +system.cpu1.numPwrStateTransitions 12326 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 6163 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 7615138435.844394 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 188025849317.388916 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 4489 72.84% 72.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1652 26.81% 99.64% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.10% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11813542449500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 6163 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 284716621891 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46932098180109 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 94433635768 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -828,6 +885,7 @@ system.cpu1.op_class::MemWrite 82163665 14.43% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 569428445 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 6003966 # number of replacements system.cpu1.dcache.tags.tagsinuse 423.687505 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 167475451 # Total number of references to valid blocks. @@ -843,6 +901,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::1 264 system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 353236361 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 353236361 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 84832048 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 84832048 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 77963660 # number of WriteReq hits @@ -915,6 +974,7 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.writebacks::writebacks 6003966 # number of writebacks system.cpu1.dcache.writebacks::total 6003966 # number of writebacks +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 4799154 # number of replacements system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 479157890 # Total number of references to valid blocks. @@ -931,6 +991,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 147 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 972714778 # Number of tag accesses system.cpu1.icache.tags.data_accesses 972714778 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 479157890 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 479157890 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 479157890 # number of demand (read+write) hits @@ -963,12 +1024,14 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 4799154 # number of writebacks system.cpu1.icache.writebacks::total 4799154 # number of writebacks +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 2283161 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13345.955021 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 14389871 # Total number of references to valid blocks. @@ -997,6 +1060,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973938 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 365657601 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 365657601 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 347777 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155733 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 503510 # number of ReadReq hits @@ -1117,6 +1181,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 378 system.cpu1.toL2Bus.snoop_filter.tot_snoops 1756231 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1756065 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 166 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 608590 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 9740544 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 5562 # Transaction distribution @@ -1154,6 +1219,7 @@ system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::total 28144557 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40301 # Transaction distribution system.iobus.trans_dist::ReadResp 40301 # Transaction distribution system.iobus.trans_dist::WriteReq 136636 # Transaction distribution @@ -1196,6 +1262,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7338888 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115590 # number of replacements system.iocache.tags.tagsinuse 11.289214 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1212,6 +1279,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040838 # Number of tag accesses system.iocache.tags.data_accesses 1040838 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses @@ -1259,6 +1327,7 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1772279 # number of replacements system.l2c.tags.tagsinuse 63191.056766 # Cycle average of tags in use system.l2c.tags.total_refs 4630026 # Total number of references to valid blocks. @@ -1297,6 +1366,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.003143 # P system.l2c.tags.occ_task_id_percent::1024 0.906433 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 73419992 # Number of tag accesses system.l2c.tags.data_accesses 73419992 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 2765418 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2765418 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 17779 # number of UpgradeReq hits @@ -1471,6 +1541,7 @@ system.membus.snoop_filter.hit_multi_requests 3224 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 82119 # Transaction distribution system.membus.trans_dist::ReadResp 569484 # Transaction distribution system.membus.trans_dist::WriteReq 38800 # Transaction distribution @@ -1513,12 +1584,21 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 4612344 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1561,16 +1641,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 11113814 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 5721773 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1636305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 133991 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 120343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 13648 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47216814802000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 82121 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 3542094 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38800 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 8deb7dd1b..fa34e1384 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.111167 # Nu sim_ticks 51111167216500 # Number of ticks simulated final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1142928 # Simulator instruction rate (inst/s) -host_op_rate 1343188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59474849541 # Simulator tick rate (ticks/s) -host_mem_usage 670860 # Number of bytes of host memory used -host_seconds 859.37 # Real time elapsed on the host +host_inst_rate 1675396 # Simulator instruction rate (inst/s) +host_op_rate 1968952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87182982694 # Simulator tick rate (ticks/s) +host_mem_usage 718784 # Number of bytes of host memory used +host_seconds 586.25 # Real time elapsed on the host sim_insts 982203438 # Number of instructions simulated sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory @@ -51,6 +52,7 @@ system.physmem.bw_total::cpu.inst 107295 # To system.physmem.bw_total::cpu.data 1466073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3617977 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -67,6 +69,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -74,6 +79,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -103,6 +109,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 266586 # Table walker walks requested system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency @@ -142,6 +149,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 351319901 # DTB hits system.cpu.dtb.misses 266586 # DTB misses system.cpu.dtb.accesses 351586487 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,6 +179,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 126834 # Table walker walks requested system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency @@ -210,6 +219,26 @@ system.cpu.itb.inst_accesses 982807118 # IT system.cpu.itb.hits 982680284 # DTB hits system.cpu.itb.misses 126834 # DTB misses system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.numPwrStateTransitions 33550 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3012440740.999106 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 59942517869.536507 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988782948204 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 577473786240 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50533693430260 # Cumulative time (in ticks) in various power states system.cpu.numCycles 102222351209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -272,6 +301,7 @@ system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1154935820 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 11606642 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. @@ -288,6 +318,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits @@ -360,6 +391,7 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks system.cpu.dcache.writebacks::total 8917390 # number of writebacks +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 14265253 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. @@ -376,6 +408,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 89 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits @@ -408,6 +441,7 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 14265253 # number of writebacks system.cpu.icache.writebacks::total 14265253 # number of writebacks +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1725806 # number of replacements system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. @@ -437,6 +471,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits @@ -557,6 +592,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution @@ -595,6 +631,7 @@ system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40242 # Transaction distribution system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -637,6 +674,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115459 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -653,6 +691,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039650 # Number of tag accesses system.iocache.tags.data_accesses 1039650 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses @@ -700,6 +739,7 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks +system.membus.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution system.membus.trans_dist::ReadResp 524946 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution @@ -742,12 +782,21 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3924997 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -790,9 +839,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167216500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index b7a4b232f..7618e4e0a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -4,15 +4,16 @@ sim_seconds 47.522770 # Nu sim_ticks 47522770414500 # Number of ticks simulated final_tick 47522770414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 771698 # Simulator instruction rate (inst/s) -host_op_rate 907739 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41601502224 # Simulator tick rate (ticks/s) -host_mem_usage 746908 # Number of bytes of host memory used -host_seconds 1142.33 # Real time elapsed on the host +host_inst_rate 967829 # Simulator instruction rate (inst/s) +host_op_rate 1138446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52174728436 # Simulator tick rate (ticks/s) +host_mem_usage 796444 # Number of bytes of host memory used +host_seconds 910.84 # Real time elapsed on the host sim_insts 881535802 # Number of instructions simulated sim_ops 1036940641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 93760 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 96448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 3323828 # Number of bytes read from this memory @@ -352,6 +353,7 @@ system.physmem_1.memoryStateTime::REF 1586889720000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 244273354008 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -378,6 +380,9 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -385,6 +390,7 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,6 +420,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 111522 # Table walker walks requested system.cpu0.dtb.walker.walksLong 111522 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12043 # Level at which table walker walks with long descriptors terminate @@ -481,6 +488,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 165523016 # DTB hits system.cpu0.dtb.misses 111522 # DTB misses system.cpu0.dtb.accesses 165634538 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -510,6 +518,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 57441 # Table walker walks requested system.cpu0.itb.walker.walksLong 57441 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 633 # Level at which table walker walks with long descriptors terminate @@ -565,6 +574,27 @@ system.cpu0.itb.inst_accesses 461257306 # IT system.cpu0.itb.hits 461199865 # DTB hits system.cpu0.itb.misses 57441 # DTB misses system.cpu0.itb.accesses 461257306 # DTB accesses +system.cpu0.numPwrStateTransitions 27854 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 13927 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3371332712.012135 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 65010943687.031532 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3873 27.81% 27.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 10023 71.97% 99.78% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 18 0.13% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988778348716 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 13927 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 570219734307 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46952550680193 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 95045540829 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -627,6 +657,7 @@ system.cpu0.op_class::MemWrite 78661954 14.53% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 541493758 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 5689621 # number of replacements system.cpu0.dcache.tags.tagsinuse 508.423656 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 159582136 # Total number of references to valid blocks. @@ -643,6 +674,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 336711039 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 336711039 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 80892970 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 80892970 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 74279623 # number of WriteReq hits @@ -839,6 +871,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183661.313684 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183661.313684 # average ReadReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 93613.644753 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 93613.644753 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 5142905 # number of replacements system.cpu0.icache.tags.tagsinuse 511.908178 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 456056448 # Total number of references to valid blocks. @@ -856,6 +889,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 927543147 # Number of tag accesses system.cpu0.icache.tags.data_accesses 927543147 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 456056448 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 456056448 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 456056448 # number of demand (read+write) hits @@ -936,12 +970,14 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.prefetcher.num_hwpf_issued 7619798 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 7619814 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 1013066 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.tags.replacements 2348165 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16134.688776 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 15333996 # Total number of references to valid blocks. @@ -977,6 +1013,7 @@ system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897705 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.tag_accesses 367708056 # Number of tag accesses system.cpu0.l2cache.tags.data_accesses 367708056 # Number of data accesses +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 263860 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148030 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 411890 # number of ReadReq hits @@ -1306,6 +1343,7 @@ system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 870 system.cpu0.toL2Bus.snoop_filter.tot_snoops 1820685 # Total number of snoops made to the snoop filter. system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1820422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 263 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu0.toL2Bus.trans_dist::ReadReq 564136 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 9642625 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 26565 # Transaction distribution @@ -1359,6 +1397,7 @@ system.cpu0.toL2Bus.respLayer2.occupancy 171545000 # La system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer3.occupancy 321847000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1388,6 +1427,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 105013 # Table walker walks requested system.cpu1.dtb.walker.walksLong 105013 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10670 # Level at which table walker walks with long descriptors terminate @@ -1449,6 +1489,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 151485069 # DTB hits system.cpu1.dtb.misses 105013 # DTB misses system.cpu1.dtb.accesses 151590082 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1478,6 +1519,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 58945 # Table walker walks requested system.cpu1.itb.walker.walksLong 58945 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 561 # Level at which table walker walks with long descriptors terminate @@ -1539,6 +1581,23 @@ system.cpu1.itb.inst_accesses 420947363 # IT system.cpu1.itb.hits 420888418 # DTB hits system.cpu1.itb.misses 58945 # DTB misses system.cpu1.itb.accesses 420947363 # DTB accesses +system.cpu1.numPwrStateTransitions 9975 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 4987 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 9429340547.425106 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 186307084392.504211 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3401 68.20% 68.20% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 1566 31.40% 99.60% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.74% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 8 0.16% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 7390880609428 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 4987 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 498649104491 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 47024121310009 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 95045540824 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1601,6 +1660,7 @@ system.cpu1.op_class::MemWrite 72249363 14.57% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 496042597 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 5018466 # number of replacements system.cpu1.dcache.tags.tagsinuse 434.493139 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 146277741 # Total number of references to valid blocks. @@ -1618,6 +1678,7 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 308017993 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 308017993 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.ReadReq_hits::cpu1.data 73753622 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 73753622 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 68485479 # number of WriteReq hits @@ -1814,6 +1875,7 @@ system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171657.272315 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171657.272315 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 82415.506439 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 82415.506439 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 4797887 # number of replacements system.cpu1.icache.tags.tagsinuse 496.259979 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 416090013 # Total number of references to valid blocks. @@ -1831,6 +1893,7 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::3 5 system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu1.icache.tags.tag_accesses 846575240 # Number of tag accesses system.cpu1.icache.tags.data_accesses 846575240 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.icache.ReadReq_hits::cpu1.inst 416090013 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 416090013 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 416090013 # number of demand (read+write) hits @@ -1911,12 +1974,14 @@ system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 92968.181818 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 92968.181818 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92968.181818 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.prefetcher.num_hwpf_issued 6995617 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 6995617 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 854583 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.tags.replacements 1970256 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13301.448664 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 14231615 # Total number of references to valid blocks. @@ -1951,6 +2016,7 @@ system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004822 system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.847717 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.tag_accesses 333785497 # Number of tag accesses system.cpu1.l2cache.tags.data_accesses 333785497 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 241732 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150683 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 392415 # number of ReadReq hits @@ -2282,6 +2348,7 @@ system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 887 system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760623 # Total number of snoops made to the snoop filter. system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 174 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.cpu1.toL2Bus.trans_dist::ReadReq 491097 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 8950741 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 11949 # Transaction distribution @@ -2335,6 +2402,7 @@ system.cpu1.toL2Bus.respLayer2.occupancy 176142000 # La system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer3.occupancy 303810499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40346 # Transaction distribution system.iobus.trans_dist::ReadResp 40346 # Transaction distribution system.iobus.trans_dist::WriteReq 136634 # Transaction distribution @@ -2411,6 +2479,7 @@ system.iobus.respLayer3.occupancy 147902000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115585 # number of replacements system.iocache.tags.tagsinuse 11.243817 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -2427,6 +2496,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040784 # Number of tag accesses system.iocache.tags.data_accesses 1040784 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses system.iocache.ReadReq_misses::total 8912 # number of ReadReq misses @@ -2552,6 +2622,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 75603.606124 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75598.897286 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75603.606124 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1336257 # number of replacements system.l2c.tags.tagsinuse 63239.486009 # Cycle average of tags in use system.l2c.tags.total_refs 5390392 # Total number of references to valid blocks. @@ -2598,6 +2669,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.003464 # P system.l2c.tags.occ_task_id_percent::1024 0.730392 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 69855982 # Number of tag accesses system.l2c.tags.data_accesses 69855982 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 2606701 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 2606701 # number of WritebackDirty hits system.l2c.UpgradeReq_hits::cpu0.data 157949 # number of UpgradeReq hits @@ -3118,6 +3190,7 @@ system.membus.snoop_filter.hit_multi_requests 3188 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 81885 # Transaction distribution system.membus.trans_dist::ReadResp 837971 # Transaction distribution system.membus.trans_dist::WriteReq 38514 # Transaction distribution @@ -3172,12 +3245,21 @@ system.membus.respLayer2.occupancy 4835085635 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 45398182 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3220,16 +3302,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 10840157 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 5896724 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1754214 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 132701 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 121224 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 11477 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47522770414500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 81887 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 4082535 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 38514 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index cc4952e71..86046cc23 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.759374 # Nu sim_ticks 51759374264500 # Number of ticks simulated final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 790659 # Simulator instruction rate (inst/s) -host_op_rate 929140 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48897567060 # Simulator tick rate (ticks/s) -host_mem_usage 670860 # Number of bytes of host memory used -host_seconds 1058.53 # Real time elapsed on the host +host_inst_rate 1051370 # Simulator instruction rate (inst/s) +host_op_rate 1235514 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65021013988 # Simulator tick rate (ticks/s) +host_mem_usage 718040 # Number of bytes of host memory used +host_seconds 796.04 # Real time elapsed on the host sim_insts 836933434 # Number of instructions simulated sim_ops 983519389 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory @@ -319,6 +320,7 @@ system.physmem_1.memoryStateTime::REF 1728359100000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -335,6 +337,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -342,6 +347,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -371,6 +377,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 187211 # Table walker walks requested system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate @@ -436,6 +443,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 300492546 # DTB hits system.cpu.dtb.misses 187211 # DTB misses system.cpu.dtb.accesses 300679757 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,6 +473,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 119486 # Table walker walks requested system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate @@ -522,6 +531,27 @@ system.cpu.itb.inst_accesses 837568735 # IT system.cpu.itb.hits 837449249 # DTB hits system.cpu.itb.misses 119486 # DTB misses system.cpu.itb.accesses 837568735 # DTB accesses +system.cpu.numPwrStateTransitions 32056 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states system.cpu.numCycles 103518748529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -584,6 +614,7 @@ system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 984078328 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9381962 # number of replacements system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. @@ -601,6 +632,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits @@ -789,6 +821,7 @@ system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13331164 # number of replacements system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. @@ -806,6 +839,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::3 6 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits @@ -886,6 +920,7 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1036266 # number of replacements system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. @@ -915,6 +950,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits @@ -1205,6 +1241,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution @@ -1255,6 +1292,7 @@ system.cpu.toL2Bus.respLayer2.occupancy 357060000 # La system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40345 # Transaction distribution system.iobus.trans_dist::ReadResp 40345 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1331,6 +1369,7 @@ system.iobus.respLayer3.occupancy 147808000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115506 # number of replacements system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1347,6 +1386,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1040073 # Number of tag accesses system.iocache.tags.data_accesses 1040073 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses @@ -1472,6 +1512,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76827 # Transaction distribution system.membus.trans_dist::ReadResp 389416 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution @@ -1525,12 +1566,21 @@ system.membus.respLayer2.occupancy 3628181019 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1573,9 +1623,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 485528e29..2c9d73210 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.111166 # Nu sim_ticks 51111166190000 # Number of ticks simulated final_tick 51111166190000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1183514 # Simulator instruction rate (inst/s) -host_op_rate 1390863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61528862033 # Simulator tick rate (ticks/s) -host_mem_usage 673932 # Number of bytes of host memory used -host_seconds 830.69 # Real time elapsed on the host +host_inst_rate 1663860 # Simulator instruction rate (inst/s) +host_op_rate 1955365 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86501229007 # Simulator tick rate (ticks/s) +host_mem_usage 721112 # Number of bytes of host memory used +host_seconds 590.87 # Real time elapsed on the host sim_insts 983128290 # Number of instructions simulated sim_ops 1155370468 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 206080 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 186880 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 3298228 # Number of bytes read from this memory @@ -69,6 +70,7 @@ system.physmem.bw_total::cpu1.inst 42799 # To system.physmem.bw_total::cpu1.data 720807 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 8515 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3617200 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -85,6 +87,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -92,6 +97,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -121,6 +127,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 145178 # Table walker walks requested system.cpu0.dtb.walker.walksLong 145178 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walkWaitTime::samples 145178 # Table walker wait (enqueue to first request) latency @@ -160,6 +167,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176040109 # DTB hits system.cpu0.dtb.misses 145178 # DTB misses system.cpu0.dtb.accesses 176185287 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,6 +197,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 70488 # Table walker walks requested system.cpu0.itb.walker.walksLong 70488 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walkWaitTime::samples 70488 # Table walker wait (enqueue to first request) latency @@ -228,6 +237,22 @@ system.cpu0.itb.inst_accesses 493231195 # IT system.cpu0.itb.hits 493160707 # DTB hits system.cpu0.itb.misses 70488 # DTB misses system.cpu0.itb.accesses 493231195 # DTB accesses +system.cpu0.numPwrStateTransitions 16910 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8455 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5871638061.761680 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 113702139546.283386 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3675 43.47% 43.47% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4716 55.78% 99.24% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.25% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.53% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 5 0.06% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.14% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 3977575082060 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8455 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1466466377805 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49644699812195 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 98036837820 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -290,6 +315,7 @@ system.cpu0.op_class::MemWrite 84152421 14.53% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 579270629 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 11609443 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 340216355 # Total number of references to valid blocks. @@ -308,6 +334,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 1418915240 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 1418915240 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 85703422 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 85585649 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 171289071 # number of ReadReq hits @@ -410,6 +437,7 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 8920157 # number of writebacks system.cpu0.dcache.writebacks::total 8920157 # number of writebacks +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 14275419 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 969443892 # Total number of references to valid blocks. @@ -428,6 +456,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 90 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 997995764 # Number of tag accesses system.cpu0.icache.tags.data_accesses 997995764 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 486058611 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 483385281 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 969443892 # number of ReadReq hits @@ -472,6 +501,7 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.writebacks::writebacks 14275419 # number of writebacks system.cpu0.icache.writebacks::total 14275419 # number of writebacks +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -501,6 +531,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 143940 # Table walker walks requested system.cpu1.dtb.walker.walksLong 143940 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walkWaitTime::samples 143940 # Table walker wait (enqueue to first request) latency @@ -540,6 +571,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 175620938 # DTB hits system.cpu1.dtb.misses 143940 # DTB misses system.cpu1.dtb.accesses 175764878 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -569,6 +601,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 69853 # Table walker walks requested system.cpu1.itb.walker.walksLong 69853 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walkWaitTime::samples 69853 # Table walker wait (enqueue to first request) latency @@ -608,6 +641,23 @@ system.cpu1.itb.inst_accesses 490500771 # IT system.cpu1.itb.hits 490430918 # DTB hits system.cpu1.itb.misses 69853 # DTB misses system.cpu1.itb.accesses 490500771 # DTB accesses +system.cpu1.numPwrStateTransitions 16606 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8303 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6010299946.497049 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 129216116342.205185 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3765 45.35% 45.35% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4474 53.88% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.02% 99.25% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 4 0.05% 99.30% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 44 0.53% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 3 0.04% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 5966367262704 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8303 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 1207645734235 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49903520455765 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 97462088232 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -670,6 +720,7 @@ system.cpu1.op_class::MemWrite 83855916 14.54% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 576734502 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40249 # Transaction distribution system.iobus.trans_dist::ReadResp 40249 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution @@ -712,6 +763,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334304 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492000 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115466 # number of replacements system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -728,6 +780,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039713 # Number of tag accesses system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses @@ -775,6 +828,7 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1725552 # number of replacements system.l2c.tags.tagsinuse 65318.589868 # Cycle average of tags in use system.l2c.tags.total_refs 46997821 # Total number of references to valid blocks. @@ -812,6 +866,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.004089 # P system.l2c.tags.occ_task_id_percent::1024 0.953751 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 426507397 # Number of tag accesses system.l2c.tags.data_accesses 426507397 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 281107 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 145752 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 278085 # number of ReadReq hits @@ -992,6 +1047,7 @@ system.membus.snoop_filter.hit_multi_requests 2893 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76679 # Transaction distribution system.membus.trans_dist::ReadResp 524759 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution @@ -1034,12 +1090,21 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 3924516 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1082,16 +1147,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 52432480 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 26546586 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1741 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 2697 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 2697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111166190000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 1321968 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23443629 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index d7be73045..d32885727 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.316243 # Nu sim_ticks 51316242679000 # Number of ticks simulated final_tick 51316242679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 408194 # Simulator instruction rate (inst/s) -host_op_rate 479646 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24400273917 # Simulator tick rate (ticks/s) -host_mem_usage 732460 # Number of bytes of host memory used -host_seconds 2103.10 # Real time elapsed on the host +host_inst_rate 414274 # Simulator instruction rate (inst/s) +host_op_rate 486791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24763727262 # Simulator tick rate (ticks/s) +host_mem_usage 734172 # Number of bytes of host memory used +host_seconds 2072.23 # Real time elapsed on the host sim_insts 858473131 # Number of instructions simulated sim_ops 1008744567 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 84032 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 93120 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 2529588 # Number of bytes read from this memory @@ -381,6 +382,7 @@ system.physmem_1.memoryStateTime::REF 1693745040000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 111730336352 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -397,6 +399,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -404,6 +409,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -433,6 +439,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 91119 # Table walker walks requested system.cpu0.dtb.walker.walksLong 91119 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walkWaitTime::samples 91119 # Table walker wait (enqueue to first request) latency @@ -474,6 +481,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 122862311 # DTB hits system.cpu0.dtb.misses 91119 # DTB misses system.cpu0.dtb.accesses 122953430 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -503,6 +511,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 53727 # Table walker walks requested system.cpu0.itb.walker.walksLong 53727 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walkWaitTime::samples 53727 # Table walker wait (enqueue to first request) latency @@ -544,6 +553,25 @@ system.cpu0.itb.inst_accesses 342570782 # IT system.cpu0.itb.hits 342517055 # DTB hits system.cpu0.itb.misses 53727 # DTB misses system.cpu0.itb.accesses 342570782 # DTB accesses +system.cpu0.numPwrStateTransitions 11952 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 5976 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8382866475.975402 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 212039540044.688660 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2476 41.43% 41.43% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3476 58.17% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 7947193331000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 5976 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1220232618571 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 50096010060429 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 413468946 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -606,6 +634,7 @@ system.cpu0.op_class::MemWrite 58357755 14.49% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 402883218 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 9811129 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 296592840 # Total number of references to valid blocks. @@ -628,6 +657,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 1256795104 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 1256795104 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 60226997 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 19487622 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 26552483 # number of ReadReq hits @@ -1013,6 +1043,7 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96262.818446 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94386.906747 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 91781.767395 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94095.700835 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 15904025 # number of replacements system.cpu0.icache.tags.tagsinuse 511.975046 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 561201521 # Total number of references to valid blocks. @@ -1035,6 +1066,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 593375053 # Number of tag accesses system.cpu0.icache.tags.data_accesses 593375053 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 337059836 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 108650316 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 66739589 # number of ReadReq hits @@ -1181,6 +1213,7 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12417.476778 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12469.061371 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12491.012251 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12470.669511 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1210,6 +1243,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 32054 # Table walker walks requested system.cpu1.dtb.walker.walksLong 32054 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4620 # Level at which table walker walks with long descriptors terminate @@ -1271,6 +1305,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 39504156 # DTB hits system.cpu1.dtb.misses 32054 # DTB misses system.cpu1.dtb.accesses 39536210 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1300,6 +1335,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 20183 # Table walker walks requested system.cpu1.itb.walker.walksLong 20183 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 931 # Level at which table walker walks with long descriptors terminate @@ -1357,6 +1393,20 @@ system.cpu1.itb.inst_accesses 110381993 # IT system.cpu1.itb.hits 110361810 # DTB hits system.cpu1.itb.misses 20183 # DTB misses system.cpu1.itb.accesses 110381993 # DTB accesses +system.cpu1.numPwrStateTransitions 6152 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 3076 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3956828120.931729 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 203372693587.464539 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 983 31.96% 31.96% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 67.95% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 11261492307001 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 3076 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 39145039379014 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171203299986 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 1184092485 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1432,6 +1482,7 @@ system.cpu2.branchPred.indirectLookups 1158254 # Nu system.cpu2.branchPred.indirectHits 808792 # Number of indirect target hits. system.cpu2.branchPred.indirectMisses 349462 # Number of indirect misses. system.cpu2.branchPredindirectMispredicted 143811 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1461,6 +1512,7 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu2.dtb.walker.walks 93613 # Table walker walks requested system.cpu2.dtb.walker.walksLong 93613 # Table walker walks initiated with long descriptors system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7056 # Level at which table walker walks with long descriptors terminate @@ -1514,6 +1566,7 @@ system.cpu2.dtb.inst_accesses 0 # IT system.cpu2.dtb.hits 53956197 # DTB hits system.cpu2.dtb.misses 93613 # DTB misses system.cpu2.dtb.accesses 54049810 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1543,6 +1596,7 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu2.itb.walker.walks 26529 # Table walker walks requested system.cpu2.itb.walker.walksLong 26529 # Table walker walks initiated with long descriptors system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1840 # Level at which table walker walks with long descriptors terminate @@ -1601,6 +1655,27 @@ system.cpu2.itb.inst_accesses 70720968 # IT system.cpu2.itb.hits 70694439 # DTB hits system.cpu2.itb.misses 26529 # DTB misses system.cpu2.itb.accesses 70720968 # DTB accesses +system.cpu2.numPwrStateTransitions 6922 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 3461 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 14586648609.314360 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 130413867074.756348 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 1099 31.75% 31.75% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 2325 67.18% 98.93% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.10% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 4 0.12% 99.22% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.25% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.31% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.36% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.39% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.42% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.45% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.48% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::overflows 18 0.52% 100.00% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::max_value 1988791943000 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 3461 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 831851842163 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 50484390836837 # Cumulative time (in ticks) in various power states system.cpu2.numCycles 1178523145 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1663,6 +1738,7 @@ system.cpu3.branchPred.indirectLookups 3035481 # Nu system.cpu3.branchPred.indirectHits 1551109 # Number of indirect target hits. system.cpu3.branchPred.indirectMisses 1484372 # Number of indirect misses. system.cpu3.branchPredindirectMispredicted 245540 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1692,6 +1768,7 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu3.dtb.walker.walks 515601 # Table walker walks requested system.cpu3.dtb.walker.walksLong 515601 # Table walker walks initiated with long descriptors system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8515 # Level at which table walker walks with long descriptors terminate @@ -1783,6 +1860,7 @@ system.cpu3.dtb.inst_accesses 0 # IT system.cpu3.dtb.hits 106537507 # DTB hits system.cpu3.dtb.misses 515601 # DTB misses system.cpu3.dtb.accesses 107053108 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1812,6 +1890,7 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.cpu3.itb.walker.walks 59193 # Table walker walks requested system.cpu3.itb.walker.walksLong 59193 # Table walker walks initiated with long descriptors system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2031 # Level at which table walker walks with long descriptors terminate @@ -1890,6 +1969,17 @@ system.cpu3.itb.inst_accesses 54084601 # IT system.cpu3.itb.hits 54025408 # DTB hits system.cpu3.itb.misses 59193 # DTB misses system.cpu3.itb.accesses 54084601 # DTB accesses +system.cpu3.numPwrStateTransitions 7272 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 3636 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 40583971.308581 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 1016609649.397212 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 2250 61.88% 61.88% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 1386 38.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::max_value 36040957368 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 3636 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 51168679359322 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 147563319678 # Cumulative time (in ticks) in various power states system.cpu3.numCycles 361836520 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -2190,6 +2280,7 @@ system.cpu3.cc_regfile_reads 71210349 # nu system.cpu3.cc_regfile_writes 71874336 # number of cc regfile writes system.cpu3.misc_regfile_reads 658260097 # number of misc regfile reads system.cpu3.misc_regfile_writes 8003769 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40273 # Transaction distribution system.iobus.trans_dist::ReadResp 40273 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution @@ -2264,6 +2355,7 @@ system.iobus.respLayer0.occupancy 41037000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 70810000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115466 # number of replacements system.iocache.tags.tagsinuse 10.425431 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -2280,6 +2372,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039713 # Number of tag accesses system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses @@ -2375,6 +2468,7 @@ system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.162969 system.iocache.demand_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.162969 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76903.162969 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1175380 # number of replacements system.l2c.tags.tagsinuse 65273.508044 # Cycle average of tags in use system.l2c.tags.total_refs 47870421 # Total number of references to valid blocks. @@ -2429,6 +2523,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.004379 # P system.l2c.tags.occ_task_id_percent::1024 0.959320 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 423637613 # Number of tag accesses system.l2c.tags.data_accesses 423637613 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 159297 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 109140 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 56643 # number of ReadReq hits @@ -3108,6 +3203,7 @@ system.membus.snoop_filter.hit_multi_requests 2739 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76738 # Transaction distribution system.membus.trans_dist::ReadResp 443894 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution @@ -3160,12 +3256,21 @@ system.membus.respLayer2.occupancy 2319703830 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 28713899 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3208,16 +3313,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 52099554 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 26383185 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 3169 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 2082 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 2082 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316242679000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 1490866 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 23977004 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index d85138b4f..b739037f9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.317219 # Nu sim_ticks 51317219225000 # Number of ticks simulated final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190793 # Simulator instruction rate (inst/s) -host_op_rate 224183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10734613908 # Simulator tick rate (ticks/s) -host_mem_usage 694152 # Number of bytes of host memory used -host_seconds 4780.54 # Real time elapsed on the host +host_inst_rate 203116 # Simulator instruction rate (inst/s) +host_op_rate 238662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11427931870 # Simulator tick rate (ticks/s) +host_mem_usage 741344 # Number of bytes of host memory used +host_seconds 4490.51 # Real time elapsed on the host sim_insts 912094204 # Number of instructions simulated sim_ops 1071714405 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory @@ -331,6 +332,7 @@ system.physmem_1.memoryStateTime::REF 1713594480000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -353,6 +355,9 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -373,6 +378,7 @@ system.cpu0.branchPred.indirectHits 2622279 # Nu system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -402,6 +408,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 931838 # Table walker walks requested system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate @@ -489,6 +496,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 187312532 # DTB hits system.cpu0.dtb.misses 931838 # DTB misses system.cpu0.dtb.accesses 188244370 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,6 +526,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 102509 # Table walker walks requested system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate @@ -594,6 +603,23 @@ system.cpu0.itb.inst_accesses 94838175 # IT system.cpu0.itb.hits 94735666 # DTB hits system.cpu0.itb.misses 102509 # DTB misses system.cpu0.itb.accesses 94838175 # DTB accesses +system.cpu0.numPwrStateTransitions 16108 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8054 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3370274965.000869 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 64926982226.426781 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3593 44.61% 44.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.18% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 1988782302928 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8054 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 24173024656883 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 27144194568117 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 677363519 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -894,6 +920,7 @@ system.cpu0.cc_regfile_reads 127089396 # nu system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 10794532 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks. @@ -912,6 +939,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits @@ -1193,6 +1221,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.022565 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 16477862 # number of replacements system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks. @@ -1211,6 +1240,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits @@ -1349,6 +1379,7 @@ system.cpu1.branchPred.indirectLookups 5144550 # Nu system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits. system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses. system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1378,6 +1409,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 920636 # Table walker walks requested system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate @@ -1470,6 +1502,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 190728754 # DTB hits system.cpu1.dtb.misses 920636 # DTB misses system.cpu1.dtb.accesses 191649390 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1499,6 +1532,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 101988 # Table walker walks requested system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate @@ -1580,6 +1614,23 @@ system.cpu1.itb.inst_accesses 95930088 # IT system.cpu1.itb.hits 95828100 # DTB hits system.cpu1.itb.misses 101988 # DTB misses system.cpu1.itb.accesses 95930088 # DTB accesses +system.cpu1.numPwrStateTransitions 16766 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8383 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 2803271183.603841 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 54004965145.463799 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3515 41.93% 41.93% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.84% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 1988782222956 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8383 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 27817396892849 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 23499822332151 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 668684774 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1880,6 +1931,7 @@ system.cpu1.cc_regfile_reads 128705619 # nu system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40297 # Transaction distribution system.iobus.trans_dist::ReadResp 40297 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1956,6 +2008,7 @@ system.iobus.respLayer3.occupancy 147712000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115457 # number of replacements system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1972,6 +2025,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039641 # Number of tag accesses system.iocache.tags.data_accesses 1039641 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses @@ -2097,6 +2151,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 75052.695090 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1414907 # number of replacements system.l2c.tags.tagsinuse 65322.046709 # Cycle average of tags in use system.l2c.tags.total_refs 51048957 # Total number of references to valid blocks. @@ -2136,6 +2191,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.004745 # P system.l2c.tags.occ_task_id_percent::1024 0.963455 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 452888307 # Number of tag accesses system.l2c.tags.data_accesses 452888307 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 548032 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 184031 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 541554 # number of ReadReq hits @@ -2620,6 +2676,7 @@ system.membus.snoop_filter.hit_multi_requests 2999 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54318 # Transaction distribution system.membus.trans_dist::ReadResp 482453 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution @@ -2673,12 +2730,21 @@ system.membus.respLayer2.occupancy 5454823379 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2721,16 +2787,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 0789be798..272c6e9a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 51.821000 # Nu sim_ticks 51820999867500 # Number of ticks simulated final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 784285 # Simulator instruction rate (inst/s) -host_op_rate 921634 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45455267989 # Simulator tick rate (ticks/s) -host_mem_usage 675212 # Number of bytes of host memory used -host_seconds 1140.04 # Real time elapsed on the host +host_inst_rate 1076689 # Simulator instruction rate (inst/s) +host_op_rate 1265246 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62402323103 # Simulator tick rate (ticks/s) +host_mem_usage 722120 # Number of bytes of host memory used +host_seconds 830.43 # Real time elapsed on the host sim_insts 894119248 # Number of instructions simulated sim_ops 1050702892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory @@ -351,6 +352,7 @@ system.physmem_1.memoryStateTime::REF 1730417000000 # T system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -367,6 +369,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -374,6 +379,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -403,6 +409,7 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.dtb.walker.walks 133030 # Table walker walks requested system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate @@ -461,6 +468,7 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 159828196 # DTB hits system.cpu0.dtb.misses 133030 # DTB misses system.cpu0.dtb.accesses 159961226 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -490,6 +498,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 78025 # Table walker walks requested system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate @@ -545,6 +554,25 @@ system.cpu0.itb.inst_accesses 446566529 # IT system.cpu0.itb.hits 446488504 # DTB hits system.cpu0.itb.misses 78025 # DTB misses system.cpu0.itb.accesses 446566529 # DTB accesses +system.cpu0.numPwrStateTransitions 16564 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 6000025981.117725 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 124621883322.639465 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3529 42.61% 42.61% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4688 56.60% 99.22% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 5700356796932 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8282 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 2128784691883 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617 # Cumulative time (in ticks) in various power states system.cpu0.numCycles 51821574278 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -607,6 +635,7 @@ system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 524698416 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 10234473 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks. @@ -626,6 +655,7 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits @@ -904,6 +934,7 @@ system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.215807 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97945.918815 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87529.813158 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92455.121930 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 13785272 # number of replacements system.cpu0.icache.tags.tagsinuse 511.891071 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 880886027 # Total number of references to valid blocks. @@ -923,6 +954,7 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.icache.tags.tag_accesses 908457605 # Number of tag accesses system.cpu0.icache.tags.data_accesses 908457605 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu0.icache.ReadReq_hits::cpu0.inst 439628868 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 441257159 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 880886027 # number of ReadReq hits @@ -1039,6 +1071,7 @@ system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1068,6 +1101,7 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu1.dtb.walker.walks 133445 # Table walker walks requested system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate @@ -1135,6 +1169,7 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 160672898 # DTB hits system.cpu1.dtb.misses 133445 # DTB misses system.cpu1.dtb.accesses 160806343 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1164,6 +1199,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 78111 # Table walker walks requested system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate @@ -1225,6 +1261,23 @@ system.cpu1.itb.inst_accesses 448261423 # IT system.cpu1.itb.hits 448183312 # DTB hits system.cpu1.itb.misses 78111 # DTB misses system.cpu1.itb.accesses 448261423 # DTB accesses +system.cpu1.numPwrStateTransitions 16084 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8042 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6194937221.007833 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 118254200557.171326 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3517 43.73% 43.73% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4458 55.43% 99.17% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.06% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 3977581677820 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8042 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2001314736155 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345 # Cumulative time (in ticks) in various power states system.cpu1.numCycles 51820425457 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1287,6 +1340,7 @@ system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 526600168 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 40318 # Transaction distribution system.iobus.trans_dist::ReadResp 40318 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1363,6 +1417,7 @@ system.iobus.respLayer3.occupancy 147754000 # La system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 115478 # number of replacements system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. @@ -1379,6 +1434,7 @@ system.iocache.tags.age_task_id_blocks_1023::3 16 system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 1039830 # Number of tag accesses system.iocache.tags.data_accesses 1039830 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses @@ -1504,6 +1560,7 @@ system.iocache.demand_avg_mshr_miss_latency::total 74462.510304 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 1307385 # number of replacements system.l2c.tags.tagsinuse 65260.397522 # Cycle average of tags in use system.l2c.tags.total_refs 44030779 # Total number of references to valid blocks. @@ -1542,6 +1599,7 @@ system.l2c.tags.occ_task_id_percent::1023 0.004333 # P system.l2c.tags.occ_task_id_percent::1024 0.958069 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 395683924 # Number of tag accesses system.l2c.tags.data_accesses 395683924 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.l2c.ReadReq_hits::cpu0.dtb.walker 246270 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 166121 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 249681 # number of ReadReq hits @@ -2004,6 +2062,7 @@ system.membus.snoop_filter.hit_multi_requests 3352 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution system.membus.trans_dist::ReadResp 450834 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution @@ -2057,12 +2116,21 @@ system.membus.respLayer2.occupancy 4926078787 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2105,16 +2173,36 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index be7e45565..c8a3d5425 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.061235 # Nu sim_ticks 61234797500 # Number of ticks simulated final_tick 61234797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196562 # Simulator instruction rate (inst/s) -host_op_rate 197541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132848546 # Simulator tick rate (ticks/s) -host_mem_usage 399976 # Number of bytes of host memory used -host_seconds 460.94 # Real time elapsed on the host +host_inst_rate 433531 # Simulator instruction rate (inst/s) +host_op_rate 435690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 293005809 # Simulator tick rate (ticks/s) +host_mem_usage 447448 # Number of bytes of host memory used +host_seconds 208.99 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory system.physmem.bytes_read::total 996672 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2044640000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1797845750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 20750031 # Number of BP lookups system.cpu.branchPred.condPredicted 17060378 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 24795 # Nu system.cpu.branchPred.indirectMisses 1410 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 61234797500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 122469595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 91054081 # Class of committed instruction system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 946097 # number of replacements system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks. @@ -443,6 +451,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits @@ -563,6 +572,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks. @@ -580,6 +590,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 740 system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits @@ -648,6 +659,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks. @@ -670,6 +682,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits @@ -820,6 +833,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution @@ -852,6 +866,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1202498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 61234797500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1029 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index d33c4ab3b..6265572cd 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.058199 # Nu sim_ticks 58199030500 # Number of ticks simulated final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218368 # Simulator instruction rate (inst/s) -host_op_rate 219455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140289424 # Simulator tick rate (ticks/s) -host_mem_usage 534192 # Number of bytes of host memory used -host_seconds 414.85 # Real time elapsed on the host +host_inst_rate 220490 # Simulator instruction rate (inst/s) +host_op_rate 221588 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 141652578 # Simulator tick rate (ticks/s) +host_mem_usage 534836 # Number of bytes of host memory used +host_seconds 410.86 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory @@ -273,6 +274,7 @@ system.physmem_1.memoryStateTime::REF 1943240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 28233538 # Number of BP lookups system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect @@ -287,6 +289,7 @@ system.cpu.branchPred.indirectHits 25478 # Nu system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -316,6 +319,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -345,6 +349,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -374,6 +379,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -404,6 +410,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 58199030500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 116398062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -693,6 +700,7 @@ system.cpu.cc_regfile_reads 369004699 # nu system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes system.cpu.misc_regfile_reads 28410103 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 5470634 # number of replacements system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. @@ -708,6 +716,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits @@ -838,6 +847,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 447 # number of replacements system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. @@ -855,6 +865,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 335 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits @@ -929,12 +940,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 248 # number of replacements system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. @@ -961,6 +974,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits @@ -1146,6 +1160,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution @@ -1184,6 +1199,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1357497 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 58199030500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 16175 # Transaction distribution system.membus.trans_dist::WritebackDirty 175 # Transaction distribution system.membus.trans_dist::CleanEvict 63 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 95463debe..b73adbdfb 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.361598 # Nu sim_ticks 361597758500 # Number of ticks simulated final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 779266 # Simulator instruction rate (inst/s) -host_op_rate 779298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1155667536 # Simulator tick rate (ticks/s) -host_mem_usage 379236 # Number of bytes of host memory used -host_seconds 312.89 # Real time elapsed on the host +host_inst_rate 1652209 # Simulator instruction rate (inst/s) +host_op_rate 1652277 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2450259534 # Simulator tick rate (ticks/s) +host_mem_usage 427260 # Number of bytes of host memory used +host_seconds 147.58 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 155576 # In system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 361597758500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 723195517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 935475 # number of replacements system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. @@ -106,6 +110,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -214,6 +219,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 25 # number of replacements system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. @@ -231,6 +237,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 781 system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -299,6 +306,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. @@ -321,6 +329,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits @@ -461,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution @@ -493,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 361597758500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 7579adace..a14ecd97e 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.065987 # Nu sim_ticks 65986743500 # Number of ticks simulated final_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84238 # Simulator instruction rate (inst/s) -host_op_rate 148330 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35183666 # Simulator tick rate (ticks/s) -host_mem_usage 410392 # Number of bytes of host memory used -host_seconds 1875.49 # Real time elapsed on the host +host_inst_rate 167131 # Simulator instruction rate (inst/s) +host_op_rate 294291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69805272 # Simulator tick rate (ticks/s) +host_mem_usage 458048 # Number of bytes of host memory used +host_seconds 945.30 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory system.physmem.bytes_read::total 1959808 # Number of bytes read from this memory @@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 2203240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 40828848 # Number of BP lookups system.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect @@ -286,8 +288,12 @@ system.cpu.branchPred.indirectHits 21202389 # Nu system.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 65986743500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 131973488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -582,6 +588,7 @@ system.cpu.cc_regfile_reads 109261684 # nu system.cpu.cc_regfile_writes 65602098 # number of cc regfile writes system.cpu.misc_regfile_reads 202573497 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2073508 # number of replacements system.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. @@ -598,6 +605,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 150 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses system.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits @@ -694,6 +702,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 93 # number of replacements system.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use system.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. @@ -712,6 +721,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 906 system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses system.cpu.icache.tags.data_accesses 59996959 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits @@ -786,6 +796,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 650 # number of replacements system.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. @@ -808,6 +819,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits @@ -950,6 +962,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 system.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution @@ -982,6 +995,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1670997 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 65986743500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1640 # Transaction distribution system.membus.trans_dist::WritebackDirty 280 # Transaction distribution system.membus.trans_dist::CleanEvict 45 # Transaction distribution diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index be41a6e0b..8ce0adaa4 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.366199 # Nu sim_ticks 366199170500 # Number of ticks simulated final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 433838 # Simulator instruction rate (inst/s) -host_op_rate 763918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1005585249 # Simulator tick rate (ticks/s) -host_mem_usage 405532 # Number of bytes of host memory used -host_seconds 364.17 # Real time elapsed on the host +host_inst_rate 926071 # Simulator instruction rate (inst/s) +host_op_rate 1630662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2146525407 # Simulator tick rate (ticks/s) +host_mem_usage 453968 # Number of bytes of host memory used +host_seconds 170.60 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1871424 # Number of bytes read from this memory system.physmem.bytes_read::total 1922816 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 17826 # To system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 366199170500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 732398341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2062733 # number of replacements system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. @@ -116,6 +123,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -204,6 +212,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24 # number of replacements system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. @@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 715 system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 435393136 # Number of tag accesses system.cpu.icache.tags.data_accesses 435393136 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 217695356 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695356 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695356 # number of demand (read+write) hits @@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 313 # number of replacements system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. @@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits @@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution @@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 366199170500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1020 # Transaction distribution system.membus.trans_dist::WritebackDirty 102 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4b67bdd9..aa609094f 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.412080 # Nu sim_ticks 412079966500 # Number of ticks simulated final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240872 # Simulator instruction rate (inst/s) -host_op_rate 240872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162212982 # Simulator tick rate (ticks/s) -host_mem_usage 251076 # Number of bytes of host memory used -host_seconds 2540.36 # Real time elapsed on the host +host_inst_rate 523017 # Simulator instruction rate (inst/s) +host_op_rate 523017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 352221098 # Simulator tick rate (ticks/s) +host_mem_usage 299640 # Number of bytes of host memory used +host_seconds 1169.95 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 13760240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123917421 # Number of BP lookups system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect @@ -329,6 +331,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 412079966500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 824159933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -375,6 +378,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 611901617 # Class of committed instruction system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535268 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. @@ -392,6 +396,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits @@ -488,6 +493,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3158 # number of replacements system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. @@ -506,6 +512,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 452106322 # Number of tag accesses system.cpu.icache.tags.data_accesses 452106322 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 226045682 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 226045682 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits @@ -574,6 +581,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 347705 # number of replacements system.cpu.l2cache.tags.tagsinuse 29504.977164 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3908748 # Total number of references to valid blocks. @@ -596,6 +604,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18756 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989685 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41820503 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41820503 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2339413 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3158 # number of WritebackClean hits @@ -742,6 +751,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution @@ -774,6 +784,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7479000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 412079966500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 173378 # Transaction distribution system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution system.membus.trans_dist::CleanEvict 51709 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 6ebc4ae73..4d23ca501 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.362632 # Nu sim_ticks 362631828500 # Number of ticks simulated final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177215 # Simulator instruction rate (inst/s) -host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126858592 # Simulator tick rate (ticks/s) -host_mem_usage 271160 # Number of bytes of host memory used -host_seconds 2858.55 # Real time elapsed on the host +host_inst_rate 379372 # Simulator instruction rate (inst/s) +host_op_rate 410911 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 271571493 # Simulator tick rate (ticks/s) +host_mem_usage 317732 # Number of bytes of host memory used +host_seconds 1335.31 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory @@ -286,6 +287,7 @@ system.physmem_1.memoryStateTime::REF 12108980000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 131880511 # Number of BP lookups system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect @@ -300,6 +302,7 @@ system.cpu.branchPred.indirectHits 3881527 # Nu system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -329,6 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,6 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,6 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -417,6 +423,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 362631828500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 725263657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -463,6 +470,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 548692589 # Class of committed instruction system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141477 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. @@ -480,6 +488,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits @@ -600,6 +609,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18130 # number of replacements system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. @@ -618,6 +628,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits @@ -686,6 +697,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112376 # number of replacements system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. @@ -708,6 +720,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits @@ -860,6 +873,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution @@ -892,6 +906,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 30027947 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 362631828500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 42981 # Transaction distribution system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution system.membus.trans_dist::CleanEvict 12558 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index b5fc0a42a..b6b8a4259 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.232865 # Nu sim_ticks 232864525000 # Number of ticks simulated final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 230904 # Simulator instruction rate (inst/s) -host_op_rate 250150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106424359 # Simulator tick rate (ticks/s) -host_mem_usage 342436 # Number of bytes of host memory used -host_seconds 2188.08 # Real time elapsed on the host +host_inst_rate 221507 # Simulator instruction rate (inst/s) +host_op_rate 239970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 102093126 # Simulator tick rate (ticks/s) +host_mem_usage 343096 # Number of bytes of host memory used +host_seconds 2280.90 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 7775820000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174583649 # Number of BP lookups system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect @@ -307,6 +309,7 @@ system.cpu.branchPred.indirectHits 4673781 # Nu system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,6 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,6 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -394,6 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,6 +430,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 465729051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -713,6 +720,7 @@ system.cpu.cc_regfile_reads 2166261838 # nu system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes system.cpu.misc_regfile_reads 217603177 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2817145 # number of replacements system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. @@ -729,6 +737,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits @@ -859,6 +868,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 76528 # number of replacements system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 17 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 395630 # number of replacements system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. @@ -985,6 +998,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits @@ -1170,6 +1184,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution @@ -1208,6 +1223,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 115689827 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 420223 # Transaction distribution system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution system.membus.trans_dist::CleanEvict 98859 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index cec661f19..826ec1511 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2212896 # Simulator instruction rate (inst/s) -host_op_rate 2396859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220336248 # Simulator tick rate (ticks/s) -host_mem_usage 304900 # Number of bytes of host memory used -host_seconds 228.92 # Real time elapsed on the host +host_inst_rate 2143205 # Simulator instruction rate (inst/s) +host_op_rate 2321375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1181904303 # Simulator tick rate (ticks/s) +host_mem_usage 305572 # Number of bytes of host memory used +host_seconds 236.37 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 773431764 # Wr system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 558721807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution system.membus.trans_dist::WriteReq 54239049 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 925783e41..59b7a6f8a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.708539 # Nu sim_ticks 708539449500 # Number of ticks simulated final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1440714 # Simulator instruction rate (inst/s) -host_op_rate 1560229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2021455048 # Simulator tick rate (ticks/s) -host_mem_usage 314896 # Number of bytes of host memory used -host_seconds 350.51 # Real time elapsed on the host +host_inst_rate 1462928 # Simulator instruction rate (inst/s) +host_op_rate 1584286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2052623495 # Simulator tick rate (ticks/s) +host_mem_usage 315564 # Number of bytes of host memory used +host_seconds 345.19 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 8701167 # To system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -344,6 +353,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. @@ -362,6 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -430,6 +441,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 110394 # number of replacements system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits @@ -597,6 +610,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution @@ -629,6 +643,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17281500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution system.membus.trans_dist::CleanEvict 11920 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index b6e16dfe3..2ac1aa390 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.481958 # Nu sim_ticks 481957625500 # Number of ticks simulated final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86883 # Simulator instruction rate (inst/s) -host_op_rate 160778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50643012 # Simulator tick rate (ticks/s) -host_mem_usage 314272 # Number of bytes of host memory used -host_seconds 9516.76 # Real time elapsed on the host +host_inst_rate 134289 # Simulator instruction rate (inst/s) +host_op_rate 248503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78275315 # Simulator tick rate (ticks/s) +host_mem_usage 362988 # Number of bytes of host memory used +host_seconds 6157.21 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 16093480000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 297786504 # Number of BP lookups system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect @@ -298,8 +300,12 @@ system.cpu.branchPred.indirectHits 119907455 # Nu system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 963915252 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -594,6 +600,7 @@ system.cpu.cc_regfile_reads 617820038 # nu system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2545945 # number of replacements system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. @@ -611,6 +618,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits @@ -707,6 +715,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4014 # number of replacements system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. @@ -725,6 +734,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits @@ -799,6 +809,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 355161 # number of replacements system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. @@ -821,6 +832,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits @@ -987,6 +999,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution @@ -1021,6 +1034,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 11087994 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 180179 # Transaction distribution system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution system.membus.trans_dist::CleanEvict 57436 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 74fbe2728..8deb96433 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 772132 # Simulator instruction rate (inst/s) -host_op_rate 1428832 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 827158459 # Simulator tick rate (ticks/s) -host_mem_usage 268696 # Number of bytes of host memory used -host_seconds 1070.86 # Real time elapsed on the host +host_inst_rate 1531547 # Simulator instruction rate (inst/s) +host_op_rate 2834130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640692833 # Simulator tick rate (ticks/s) +host_mem_usage 315956 # Number of bytes of host memory used +host_seconds 539.88 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 1119742368 # Wr system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1771545853 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution system.membus.trans_dist::WriteReq 149158211 # Transaction distribution diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 4d088ccd8..38495841e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.650501 # Nu sim_ticks 1650501252500 # Number of ticks simulated final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 482495 # Simulator instruction rate (inst/s) -host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 963127288 # Simulator tick rate (ticks/s) -host_mem_usage 277668 # Number of bytes of host memory used -host_seconds 1713.69 # Real time elapsed on the host +host_inst_rate 943240 # Simulator instruction rate (inst/s) +host_op_rate 1745467 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1882837072 # Simulator tick rate (ticks/s) +host_mem_usage 326104 # Number of bytes of host memory used +host_seconds 876.60 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11369424 # To system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 3301002505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. @@ -223,6 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -291,6 +301,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 348438 # number of replacements system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. @@ -312,6 +323,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits @@ -458,6 +470,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution @@ -490,6 +503,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 174499 # Transaction distribution system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index f8a01c82f..1c291ca67 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.223533 # Nu sim_ticks 223532962500 # Number of ticks simulated final_tick 223532962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 234970 # Simulator instruction rate (inst/s) -host_op_rate 234970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131748654 # Simulator tick rate (ticks/s) -host_mem_usage 255168 # Number of bytes of host memory used -host_seconds 1696.66 # Real time elapsed on the host +host_inst_rate 488740 # Simulator instruction rate (inst/s) +host_op_rate 488740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274038351 # Simulator tick rate (ticks/s) +host_mem_usage 302272 # Number of bytes of host memory used +host_seconds 815.70 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory system.physmem.bytes_read::total 503680 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 7464080000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1017823750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 45898041 # Number of BP lookups system.cpu.branchPred.condPredicted 26691639 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 566044 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 223532962500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 447065925 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 398664665 # Class of committed instruction system.cpu.tickCycles 443407678 # Number of cycles that the object actually ticked system.cpu.idleCycles 3658247 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 771 # number of replacements system.cpu.dcache.tags.tagsinuse 3291.617120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 167826980 # Total number of references to valid blocks. @@ -361,6 +365,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 335672353 # Number of tag accesses system.cpu.dcache.tags.data_accesses 335672353 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94312181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94312181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73514799 # number of WriteReq hits @@ -457,6 +462,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463 system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3190 # number of replacements system.cpu.icache.tags.tagsinuse 1919.630000 # Cycle average of tags in use system.cpu.icache.tags.total_refs 96785699 # Total number of references to valid blocks. @@ -474,6 +480,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 193586902 # Number of tag accesses system.cpu.icache.tags.data_accesses 193586902 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 96785699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 96785699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 96785699 # number of demand (read+write) hits @@ -542,6 +549,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495 system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4421.902302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4798 # Total number of references to valid blocks. @@ -563,6 +571,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 114820 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 114820 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3190 # number of WritebackClean hits @@ -703,6 +712,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 6135 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3190 # Transaction distribution @@ -735,6 +745,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7752000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 223532962500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d9eeb4f16..68a991d52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.064189 # Nu sim_ticks 64188759000 # Number of ticks simulated final_tick 64188759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189145 # Simulator instruction rate (inst/s) -host_op_rate 189145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32326376 # Simulator tick rate (ticks/s) -host_mem_usage 256256 # Number of bytes of host memory used -host_seconds 1985.65 # Real time elapsed on the host +host_inst_rate 392159 # Simulator instruction rate (inst/s) +host_op_rate 392159 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67023124 # Simulator tick rate (ticks/s) +host_mem_usage 303292 # Number of bytes of host memory used +host_seconds 957.71 # Real time elapsed on the host sim_insts 375574794 # Number of instructions simulated sim_ops 375574794 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory system.physmem.bytes_read::total 476160 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 2143180000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 684265000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 47858697 # Number of BP lookups system.cpu.branchPred.condPredicted 27887013 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 573168 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 64188759000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 128377521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -590,6 +593,7 @@ system.cpu.fp_regfile_reads 154536644 # nu system.cpu.fp_regfile_writes 102074619 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776 # number of replacements system.cpu.dcache.tags.tagsinuse 3292.009184 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 152572889 # Total number of references to valid blocks. @@ -608,6 +612,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 305192990 # Number of tag accesses system.cpu.dcache.tags.data_accesses 305192990 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 79071847 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 79071847 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501036 # number of WriteReq hits @@ -708,6 +713,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839 system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2132 # number of replacements system.cpu.icache.tags.tagsinuse 1831.246133 # Cycle average of tags in use system.cpu.icache.tags.total_refs 46954666 # Total number of references to valid blocks. @@ -725,6 +731,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 93924682 # Number of tag accesses system.cpu.icache.tags.data_accesses 93924682 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 46954666 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 46954666 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 46954666 # number of demand (read+write) hits @@ -799,6 +806,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384 system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4001.708243 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3078 # Total number of references to valid blocks. @@ -820,6 +828,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4032 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 97187 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 97187 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits @@ -960,6 +969,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5048 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution @@ -992,6 +1002,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 6090499 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6264000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 64188759000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4312 # Transaction distribution system.membus.trans_dist::ReadExReq 3128 # Transaction distribution system.membus.trans_dist::ReadExResp 3128 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index fe4a94641..d0130300a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.567385 # Nu sim_ticks 567385356500 # Number of ticks simulated final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 857568 # Simulator instruction rate (inst/s) -host_op_rate 857568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220503073 # Simulator tick rate (ticks/s) -host_mem_usage 253440 # Number of bytes of host memory used -host_seconds 464.88 # Real time elapsed on the host +host_inst_rate 1687815 # Simulator instruction rate (inst/s) +host_op_rate 1687815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2402123351 # Simulator tick rate (ticks/s) +host_mem_usage 300208 # Number of bytes of host memory used +host_seconds 236.20 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 361518 # In system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 567385356500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1134770713 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 764 # number of replacements system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. @@ -139,6 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits @@ -227,6 +232,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1769 # number of replacements system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. @@ -245,6 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -313,6 +320,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. @@ -335,6 +343,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits @@ -475,6 +484,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution @@ -507,6 +517,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 567385356500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4032 # Transaction distribution system.membus.trans_dist::ReadExReq 3142 # Transaction distribution system.membus.trans_dist::ReadExResp 3142 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 787a34237..521f1135c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.211715 # Nu sim_ticks 211714953000 # Number of ticks simulated final_tick 211714953000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119593 # Simulator instruction rate (inst/s) -host_op_rate 143584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92732901 # Simulator tick rate (ticks/s) -host_mem_usage 275300 # Number of bytes of host memory used -host_seconds 2283.06 # Real time elapsed on the host +host_inst_rate 271910 # Simulator instruction rate (inst/s) +host_op_rate 326458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 210840466 # Simulator tick rate (ticks/s) +host_mem_usage 322892 # Number of bytes of host memory used +host_seconds 1004.15 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory system.physmem.bytes_read::total 485504 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 7069400000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1682763000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 32413931 # Number of BP lookups system.cpu.branchPred.condPredicted 16919661 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 738142 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 2264485 # Nu system.cpu.branchPred.indirectMisses 39407 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 211714953000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 423429906 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 327812214 # Class of committed instruction system.cpu.tickCycles 420106568 # Number of cycles that the object actually ticked system.cpu.idleCycles 3323338 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements system.cpu.dcache.tags.tagsinuse 3085.570959 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168654881 # Total number of references to valid blocks. @@ -445,6 +453,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 337328856 # Number of tag accesses system.cpu.dcache.tags.data_accesses 337328856 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86522107 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86522107 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047451 # number of WriteReq hits @@ -565,6 +574,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867 system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 38168 # number of replacements system.cpu.icache.tags.tagsinuse 1923.744161 # Cycle average of tags in use system.cpu.icache.tags.total_refs 69641436 # Total number of references to valid blocks. @@ -583,6 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1483 system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 139403186 # Number of tag accesses system.cpu.icache.tags.data_accesses 139403186 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 69641436 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 69641436 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 69641436 # number of demand (read+write) hits @@ -651,6 +662,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314 system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 4199.701287 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 60529 # Total number of references to valid blocks. @@ -673,6 +685,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4262 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172363 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 561366 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 561366 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23251 # number of WritebackClean hits @@ -823,6 +836,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15034 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 41746 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 38168 # Transaction distribution @@ -855,6 +869,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 60156998 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 211714953000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 14b00e16f..f64410488 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.111754 # Nu sim_ticks 111753553500 # Number of ticks simulated final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210028 # Simulator instruction rate (inst/s) -host_op_rate 252162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85964130 # Simulator tick rate (ticks/s) -host_mem_usage 334160 # Number of bytes of host memory used -host_seconds 1300.00 # Real time elapsed on the host +host_inst_rate 201687 # Simulator instruction rate (inst/s) +host_op_rate 242148 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82550264 # Simulator tick rate (ticks/s) +host_mem_usage 334820 # Number of bytes of host memory used +host_seconds 1353.76 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory @@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF 3731520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 35971731 # Number of BP lookups system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect @@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits 2473442 # Nu system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 111753553500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 223507108 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -676,6 +683,7 @@ system.cpu.cc_regfile_reads 1279432977 # nu system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes system.cpu.misc_regfile_reads 1056766060 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1542955 # number of replacements system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. @@ -693,6 +701,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits @@ -823,6 +832,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 726201 # number of replacements system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. @@ -841,6 +851,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 69 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits @@ -915,12 +926,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. @@ -948,6 +961,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits @@ -1132,6 +1146,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution @@ -1167,6 +1182,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 111753553500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 83887 # Transaction distribution system.membus.trans_dist::UpgradeReq 13 # Transaction distribution system.membus.trans_dist::ReadExReq 730 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index ae8086be1..ddaf7206c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.201717 # Nu sim_ticks 201717314000 # Number of ticks simulated final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1495302 # Simulator instruction rate (inst/s) -host_op_rate 1795276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1104713261 # Simulator tick rate (ticks/s) -host_mem_usage 309028 # Number of bytes of host memory used -host_seconds 182.60 # Real time elapsed on the host +host_inst_rate 1421524 # Simulator instruction rate (inst/s) +host_op_rate 1706697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1050207028 # Simulator tick rate (ticks/s) +host_mem_usage 310740 # Number of bytes of host memory used +host_seconds 192.07 # Real time elapsed on the host sim_insts 273037595 # Number of instructions simulated sim_ops 327811950 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1983209845 # Wr system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 403434629 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812145 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 434895828 # Transaction distribution system.membus.trans_dist::ReadResp 434906723 # Transaction distribution system.membus.trans_dist::WriteReq 82052672 # Transaction distribution diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index fadffed88..ea2a43ab9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.517291 # Nu sim_ticks 517291025500 # Number of ticks simulated final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 977708 # Simulator instruction rate (inst/s) -host_op_rate 1173775 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1854370201 # Simulator tick rate (ticks/s) -host_mem_usage 319164 # Number of bytes of host memory used -host_seconds 278.96 # Real time elapsed on the host +host_inst_rate 968617 # Simulator instruction rate (inst/s) +host_op_rate 1162861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1837127354 # Simulator tick rate (ticks/s) +host_mem_usage 320856 # Number of bytes of host memory used +host_seconds 281.58 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 322666 # In system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 517291025500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1034582051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1332 # number of replacements system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. @@ -225,6 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits @@ -343,6 +352,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13796 # number of replacements system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. @@ -361,6 +371,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits @@ -429,6 +440,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. @@ -451,6 +463,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits @@ -591,6 +604,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution @@ -623,6 +637,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 23404500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 517291025500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3976 # Transaction distribution system.membus.trans_dist::ReadExReq 2856 # Transaction distribution system.membus.trans_dist::ReadExResp 2856 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 30b536776..383495cbc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.504258 # Nu sim_ticks 504258263000 # Number of ticks simulated final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254365 # Simulator instruction rate (inst/s) -host_op_rate 254365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138099861 # Simulator tick rate (ticks/s) -host_mem_usage 257972 # Number of bytes of host memory used -host_seconds 3651.40 # Real time elapsed on the host +host_inst_rate 532728 # Simulator instruction rate (inst/s) +host_op_rate 532728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 289228716 # Simulator tick rate (ticks/s) +host_mem_usage 306284 # Number of bytes of host memory used +host_seconds 1743.46 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory @@ -278,6 +279,7 @@ system.physmem_1.memoryStateTime::REF 16838120000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 123840342 # Number of BP lookups system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect @@ -325,6 +327,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 504258263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1008516526 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -371,6 +374,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 928789150 # Class of committed instruction system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776530 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. @@ -389,6 +393,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits @@ -485,6 +490,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10567 # number of replacements system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. @@ -503,6 +509,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits @@ -571,6 +578,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 259940 # number of replacements system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. @@ -593,6 +601,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits @@ -739,6 +748,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution @@ -771,6 +781,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 18463500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225622 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution system.membus.trans_dist::CleanEvict 191176 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 597ecfa0d..82cf197ab 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.174766 # Nu sim_ticks 174766258500 # Number of ticks simulated final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186758 # Simulator instruction rate (inst/s) -host_op_rate 186758 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38746139 # Simulator tick rate (ticks/s) -host_mem_usage 259692 # Number of bytes of host memory used -host_seconds 4510.55 # Real time elapsed on the host +host_inst_rate 383088 # Simulator instruction rate (inst/s) +host_op_rate 383088 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79477968 # Simulator tick rate (ticks/s) +host_mem_usage 307308 # Number of bytes of host memory used +host_seconds 2198.93 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory @@ -277,6 +278,7 @@ system.physmem_1.memoryStateTime::REF 5835700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 129267026 # Number of BP lookups system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect @@ -324,6 +326,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 174766258500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 349532518 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -616,6 +619,7 @@ system.cpu.fp_regfile_reads 36406853 # nu system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776668 # number of replacements system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. @@ -634,6 +638,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits @@ -734,6 +739,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4617 # number of replacements system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. @@ -752,6 +758,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits @@ -826,6 +833,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 259794 # number of replacements system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. @@ -848,6 +856,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits @@ -994,6 +1003,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution @@ -1026,6 +1036,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 9483000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 174766258500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225541 # Transaction distribution system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution system.membus.trans_dist::CleanEvict 191110 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index b67898874..31542f021 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.464395 # Nu sim_ticks 464394627000 # Number of ticks simulated final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1449486 # Simulator instruction rate (inst/s) -host_op_rate 1449486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 724900195 # Simulator tick rate (ticks/s) -host_mem_usage 247720 # Number of bytes of host memory used -host_seconds 640.63 # Real time elapsed on the host +host_inst_rate 3142131 # Simulator instruction rate (inst/s) +host_op_rate 3142131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1571406745 # Simulator tick rate (ticks/s) +host_mem_usage 294224 # Number of bytes of host memory used +host_seconds 295.53 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1588466830 # Wr system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 928789255 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution system.membus.trans_dist::WriteReq 98301200 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f1f838fe1..ba8d8610f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.288319 # Nu sim_ticks 1288319411500 # Number of ticks simulated final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 888638 # Simulator instruction rate (inst/s) -host_op_rate 888638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1232892743 # Simulator tick rate (ticks/s) -host_mem_usage 256432 # Number of bytes of host memory used -host_seconds 1044.96 # Real time elapsed on the host +host_inst_rate 1791468 # Simulator instruction rate (inst/s) +host_op_rate 1791468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2485477121 # Simulator tick rate (ticks/s) +host_mem_usage 303212 # Number of bytes of host memory used +host_seconds 518.34 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 3312619 # To system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2576638823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 776432 # number of replacements system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4618 # number of replacements system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. @@ -251,6 +257,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits @@ -319,6 +326,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258847 # number of replacements system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. @@ -341,6 +349,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits @@ -487,6 +496,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution @@ -519,6 +529,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1288319411500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 224741 # Transaction distribution system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution system.membus.trans_dist::CleanEvict 190447 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 3ea3d5388..eb3e6af6a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.489946 # Nu sim_ticks 489945697500 # Number of ticks simulated final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152136 # Simulator instruction rate (inst/s) -host_op_rate 187299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116346895 # Simulator tick rate (ticks/s) -host_mem_usage 275904 # Number of bytes of host memory used -host_seconds 4211.08 # Real time elapsed on the host +host_inst_rate 287135 # Simulator instruction rate (inst/s) +host_op_rate 353501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 219588415 # Simulator tick rate (ticks/s) +host_mem_usage 322476 # Number of bytes of host memory used +host_seconds 2231.20 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory @@ -272,6 +273,7 @@ system.physmem_1.memoryStateTime::REF 16360240000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 144591747 # Number of BP lookups system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect @@ -286,6 +288,7 @@ system.cpu.branchPred.indirectHits 15989167 # Nu system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -315,6 +318,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -344,6 +348,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -373,6 +378,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -403,6 +409,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 979891395 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -449,6 +456,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 788730744 # Class of committed instruction system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778302 # number of replacements system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. @@ -467,6 +475,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits @@ -587,6 +596,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24859 # number of replacements system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. @@ -603,6 +613,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits @@ -671,6 +682,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258808 # number of replacements system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. @@ -693,6 +705,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits @@ -845,6 +858,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution @@ -877,6 +891,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 39920495 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225121 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190682 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index a4f9b9a0f..77ad5d4bc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.326731 # Nu sim_ticks 326731324000 # Number of ticks simulated final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188423 # Simulator instruction rate (inst/s) -host_op_rate 231974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96095829 # Simulator tick rate (ticks/s) -host_mem_usage 319396 # Number of bytes of host memory used -host_seconds 3400.06 # Real time elapsed on the host +host_inst_rate 187465 # Simulator instruction rate (inst/s) +host_op_rate 230795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95607340 # Simulator tick rate (ticks/s) +host_mem_usage 320048 # Number of bytes of host memory used +host_seconds 3417.43 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory @@ -295,6 +296,7 @@ system.physmem_1.memoryStateTime::REF 10910120000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174663372 # Number of BP lookups system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect @@ -309,6 +311,7 @@ system.cpu.branchPred.indirectHits 16701520 # Nu system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -338,6 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -367,6 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,6 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,6 +432,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 653462649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -716,6 +723,7 @@ system.cpu.cc_regfile_reads 3322370942 # nu system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2756452 # number of replacements system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits @@ -863,6 +872,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1979880 # number of replacements system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. @@ -880,6 +890,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 333 system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits @@ -954,12 +965,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 301370 # number of replacements system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. @@ -986,6 +999,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits @@ -1167,6 +1181,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution @@ -1202,6 +1217,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 951856 # Transaction distribution system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution system.membus.trans_dist::CleanEvict 227102 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 1251990c8..e2d47dff8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843468 # Simulator instruction rate (inst/s) -host_op_rate 2269552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138694237 # Simulator tick rate (ticks/s) -host_mem_usage 309656 # Number of bytes of host memory used -host_seconds 347.53 # Real time elapsed on the host +host_inst_rate 1817115 # Simulator instruction rate (inst/s) +host_op_rate 2237108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1122416416 # Simulator tick rate (ticks/s) +host_mem_usage 311336 # Number of bytes of host memory used +host_seconds 352.57 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 1322421027 # Wr system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 791453558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 893703778 # Transaction distribution system.membus.trans_dist::ReadResp 893709517 # Transaction distribution system.membus.trans_dist::WriteReq 128951477 # Transaction distribution diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 0aed4ec36..fc47d4b38 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.045756 # Nu sim_ticks 1045756396500 # Number of ticks simulated final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1156934 # Simulator instruction rate (inst/s) -host_op_rate 1421363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1892295085 # Simulator tick rate (ticks/s) -host_mem_usage 319640 # Number of bytes of host memory used -host_seconds 552.64 # Real time elapsed on the host +host_inst_rate 1150404 # Simulator instruction rate (inst/s) +host_op_rate 1413341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1881615398 # Simulator tick rate (ticks/s) +host_mem_usage 320304 # Number of bytes of host memory used +host_seconds 555.78 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 4045179 # To system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2091512793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778046 # number of replacements system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits @@ -350,6 +359,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 8769 # number of replacements system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. @@ -366,6 +376,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits @@ -434,6 +445,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 257772 # number of replacements system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. @@ -456,6 +468,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits @@ -598,6 +611,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution @@ -630,6 +644,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 15312000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1045756396500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 224275 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190094 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 48bad98ae..7d04a6897 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.059447 # Nu sim_ticks 59447065000 # Number of ticks simulated final_tick 59447065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 249746 # Simulator instruction rate (inst/s) -host_op_rate 249746 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167876675 # Simulator tick rate (ticks/s) -host_mem_usage 256840 # Number of bytes of host memory used -host_seconds 354.11 # Real time elapsed on the host +host_inst_rate 518825 # Simulator instruction rate (inst/s) +host_op_rate 518825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 348748418 # Simulator tick rate (ticks/s) +host_mem_usage 305412 # Number of bytes of host memory used +host_seconds 170.46 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 432832 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10149568 # Number of bytes read from this memory system.physmem.bytes_read::total 10582400 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 1984840000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 17372590500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14660042 # Number of BP lookups system.cpu.branchPred.condPredicted 9484785 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 381684 # Number of conditional branches incorrect @@ -326,6 +328,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 59447065000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 118894130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -372,6 +375,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 88438073 # Class of committed instruction system.cpu.tickCycles 91425505 # Number of cycles that the object actually ticked system.cpu.idleCycles 27468625 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 200766 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.673886 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34612040 # Total number of references to valid blocks. @@ -388,6 +392,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70168000 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70168000 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20278781 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20278781 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14333259 # number of WriteReq hits @@ -484,6 +489,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 152872 # number of replacements system.cpu.icache.tags.tagsinuse 1932.382407 # Cycle average of tags in use system.cpu.icache.tags.total_refs 25430610 # Total number of references to valid blocks. @@ -502,6 +508,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 798 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 51325982 # Number of tag accesses system.cpu.icache.tags.data_accesses 51325982 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 25430610 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25430610 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25430610 # number of demand (read+write) hits @@ -570,6 +577,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334 system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 133382 # number of replacements system.cpu.l2cache.tags.tagsinuse 30429.048447 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 403995 # Total number of references to valid blocks. @@ -592,6 +600,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 124 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 6016424 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 6016424 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168424 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168424 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 152872 # number of WritebackClean hits @@ -738,6 +747,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 4037 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 216218 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 282893 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 152872 # Transaction distribution @@ -770,6 +780,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 232381497 # La system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 307297491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 59447065000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 34467 # Transaction distribution system.membus.trans_dist::WritebackDirty 114469 # Transaction distribution system.membus.trans_dist::CleanEvict 14990 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7587af834..a7431aca8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.022275 # Nu sim_ticks 22275010500 # Number of ticks simulated final_tick 22275010500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168633 # Simulator instruction rate (inst/s) -host_op_rate 168633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47194651 # Simulator tick rate (ticks/s) -host_mem_usage 258376 # Number of bytes of host memory used -host_seconds 471.98 # Real time elapsed on the host +host_inst_rate 330986 # Simulator instruction rate (inst/s) +host_op_rate 330986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 92631737 # Simulator tick rate (ticks/s) +host_mem_usage 306452 # Number of bytes of host memory used +host_seconds 240.47 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 743600000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 9336732250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 16474744 # Number of BP lookups system.cpu.branchPred.condPredicted 10670267 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 324432 # Number of conditional branches incorrect @@ -326,6 +328,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 22275010500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 44550025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -620,6 +623,7 @@ system.cpu.fp_regfile_reads 255567 # nu system.cpu.fp_regfile_writes 240367 # number of floating regfile writes system.cpu.misc_regfile_reads 38271 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 201418 # number of replacements system.cpu.dcache.tags.tagsinuse 4070.642288 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 33984828 # Total number of references to valid blocks. @@ -636,6 +640,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 1244 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 70818146 # Number of tag accesses system.cpu.dcache.tags.data_accesses 70818146 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20423642 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20423642 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13561123 # number of WriteReq hits @@ -736,6 +741,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912 system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 90292 # number of replacements system.cpu.icache.tags.tagsinuse 1916.963164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 13622372 # Total number of references to valid blocks. @@ -754,6 +760,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 384 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 27546828 # Number of tag accesses system.cpu.icache.tags.data_accesses 27546828 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 13622372 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13622372 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13622372 # number of demand (read+write) hits @@ -828,6 +835,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897 system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 133082 # number of replacements system.cpu.l2cache.tags.tagsinuse 30595.837110 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 280630 # Total number of references to valid blocks. @@ -850,6 +858,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979401 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 5025086 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 5025086 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 168806 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 168806 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 90292 # number of WritebackClean hits @@ -996,6 +1005,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 4045 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 154463 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 283225 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 90292 # Transaction distribution @@ -1028,6 +1038,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 138521976 # La system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 308281978 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 22275010500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 34270 # Transaction distribution system.membus.trans_dist::WritebackDirty 114419 # Transaction distribution system.membus.trans_dist::CleanEvict 14728 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c91d712f2..4b73022fa 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.056803 # Nu sim_ticks 56802974500 # Number of ticks simulated final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132517 # Simulator instruction rate (inst/s) -host_op_rate 169470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106146312 # Simulator tick rate (ticks/s) -host_mem_usage 275700 # Number of bytes of host memory used -host_seconds 535.14 # Real time elapsed on the host +host_inst_rate 307576 # Simulator instruction rate (inst/s) +host_op_rate 393344 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 246367888 # Simulator tick rate (ticks/s) +host_mem_usage 323312 # Number of bytes of host memory used +host_seconds 230.56 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory @@ -279,6 +280,7 @@ system.physmem_1.memoryStateTime::REF 1896700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 14774616 # Number of BP lookups system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect @@ -293,6 +295,7 @@ system.cpu.branchPred.indirectHits 157999 # Nu system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +325,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +355,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -380,6 +385,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -410,6 +416,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 56802974500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 113605949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -456,6 +463,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 90690106 # Class of committed instruction system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156448 # number of replacements system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. @@ -472,6 +480,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits @@ -592,6 +601,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43497 # number of replacements system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. @@ -609,6 +619,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits @@ -677,6 +688,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 96391 # number of replacements system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. @@ -699,6 +711,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits @@ -855,6 +868,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution @@ -887,6 +901,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 68328959 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26002 # Transaction distribution system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution system.membus.trans_dist::CleanEvict 6912 # Transaction distribution diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index f186d41b5..778d6ee7e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.033525 # Nu sim_ticks 33524756000 # Number of ticks simulated final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201547 # Simulator instruction rate (inst/s) -host_op_rate 257754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95290096 # Simulator tick rate (ticks/s) -host_mem_usage 324320 # Number of bytes of host memory used -host_seconds 351.82 # Real time elapsed on the host +host_inst_rate 198459 # Simulator instruction rate (inst/s) +host_op_rate 253806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93830272 # Simulator tick rate (ticks/s) +host_mem_usage 324968 # Number of bytes of host memory used +host_seconds 357.29 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory @@ -282,6 +283,7 @@ system.physmem_1.memoryStateTime::REF 1119300000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 17055826 # Number of BP lookups system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect @@ -296,6 +298,7 @@ system.cpu.branchPred.indirectHits 195217 # Nu system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -325,6 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -354,6 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,6 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,6 +419,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 67049513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -703,6 +710,7 @@ system.cpu.cc_regfile_reads 345209533 # nu system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes system.cpu.misc_regfile_reads 44112661 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 486293 # number of replacements system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. @@ -718,6 +726,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits @@ -848,6 +857,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 325000 # number of replacements system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. @@ -866,6 +876,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 7 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits @@ -940,12 +951,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 128177 # number of replacements system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. @@ -972,6 +985,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits @@ -1153,6 +1167,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution @@ -1188,6 +1203,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 488687208 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 144751 # Transaction distribution system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution system.membus.trans_dist::CleanEvict 28117 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index a81e64eec..e74f79662 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.208778 # Nu sim_ticks 1208777694500 # Number of ticks simulated final_tick 1208777694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239767 # Simulator instruction rate (inst/s) -host_op_rate 239767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158688267 # Simulator tick rate (ticks/s) -host_mem_usage 248760 # Number of bytes of host memory used -host_seconds 7617.31 # Real time elapsed on the host +host_inst_rate 530685 # Simulator instruction rate (inst/s) +host_op_rate 530685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 351230785 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 3441.55 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124970112 # Number of bytes read from this memory system.physmem.bytes_read::total 125031424 # Number of bytes read from this memory @@ -293,6 +294,7 @@ system.physmem_1.memoryStateTime::REF 40363700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 587184084000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 246097965 # Number of BP lookups system.cpu.branchPred.condPredicted 186356162 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15588061 # Number of conditional branches incorrect @@ -340,6 +342,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2417555389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -386,6 +389,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1826378509 # Class of committed instruction system.cpu.tickCycles 2075251932 # Number of cycles that the object actually ticked system.cpu.idleCycles 342303457 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9121974 # number of replacements system.cpu.dcache.tags.tagsinuse 4080.726355 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 601538856 # Total number of references to valid blocks. @@ -403,6 +407,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1231275880 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1231275880 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 443056865 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 443056865 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158481991 # number of WriteReq hits @@ -499,6 +504,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194 system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 750.173547 # Cycle average of tags in use system.cpu.icache.tags.total_refs 597988654 # Total number of references to valid blocks. @@ -514,6 +520,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 874 system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1195980182 # Number of tag accesses system.cpu.icache.tags.data_accesses 1195980182 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 597988654 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 597988654 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 597988654 # number of demand (read+write) hits @@ -582,6 +589,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916 system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1920891 # number of replacements system.cpu.l2cache.tags.tagsinuse 30765.315888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14409692 # Total number of references to valid blocks. @@ -604,6 +612,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15532 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909576 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149830076 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149830076 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3686603 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits @@ -746,6 +755,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7239688 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4708742 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution @@ -778,6 +788,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1437000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13689105000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1208777694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1173106 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022139 # Transaction distribution system.membus.trans_dist::CleanEvict 897726 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 12610c445..6c06e7b34 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.669588 # Nu sim_ticks 669587683000 # Number of ticks simulated final_tick 669587683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147374 # Simulator instruction rate (inst/s) -host_op_rate 147374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56841738 # Simulator tick rate (ticks/s) -host_mem_usage 250296 # Number of bytes of host memory used -host_seconds 11779.86 # Real time elapsed on the host +host_inst_rate 268815 # Simulator instruction rate (inst/s) +host_op_rate 268815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103681118 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 6458.15 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125489536 # Number of bytes read from this memory system.physmem.bytes_read::total 125550272 # Number of bytes read from this memory @@ -308,6 +309,7 @@ system.physmem_1.memoryStateTime::REF 22358960000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 434911888500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 409349783 # Number of BP lookups system.cpu.branchPred.condPredicted 318159413 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15962959 # Number of conditional branches incorrect @@ -355,6 +357,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 669587683000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1339175367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -647,6 +650,7 @@ system.cpu.fp_regfile_reads 39668 # nu system.cpu.fp_regfile_writes 612 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9207202 # number of replacements system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks. @@ -664,6 +668,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits @@ -780,6 +785,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks. @@ -796,6 +802,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 882 system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits @@ -870,6 +877,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1929018 # number of replacements system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks. @@ -892,6 +900,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -1034,6 +1043,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -1066,6 +1076,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1423999 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13816947000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 669587683000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1189304 # Transaction distribution system.membus.trans_dist::WritebackDirty 1024304 # Transaction distribution system.membus.trans_dist::CleanEvict 903679 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 01aa62af6..1bae4420d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1469307 # Simulator instruction rate (inst/s) -host_op_rate 1469307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 737317476 # Simulator tick rate (ticks/s) -host_mem_usage 238516 # Number of bytes of host memory used -host_seconds 1238.53 # Real time elapsed on the host +host_inst_rate 3169811 # Simulator instruction rate (inst/s) +host_op_rate 3169811 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1590652371 # Simulator tick rate (ticks/s) +host_mem_usage 285272 # Number of bytes of host memory used +host_seconds 574.10 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution system.membus.trans_dist::WriteReq 160728502 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index e31f2fa37..d98d61e9c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.636720 # Nu sim_ticks 2636719559500 # Number of ticks simulated final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 874013 # Simulator instruction rate (inst/s) -host_op_rate 874013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1266376533 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 2082.10 # Real time elapsed on the host +host_inst_rate 1821657 # Simulator instruction rate (inst/s) +host_op_rate 1821657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2639438336 # Simulator tick rate (ticks/s) +host_mem_usage 295280 # Number of bytes of host memory used +host_seconds 998.97 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124892160 # Number of bytes read from this memory system.physmem.bytes_read::total 124943488 # Number of bytes read from this memory @@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks 24805660 # To system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,6 +72,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9107638 # number of replacements system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. @@ -146,6 +150,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits @@ -234,6 +239,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. @@ -250,6 +256,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 730 system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -318,6 +325,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919525 # number of replacements system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. @@ -340,6 +348,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -482,6 +491,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution @@ -514,6 +524,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2636719559500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169857 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 836b1fb8a..d91451297 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 1.116866 # Nu sim_ticks 1116865668500 # Number of ticks simulated final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243832 # Simulator instruction rate (inst/s) -host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176313668 # Simulator tick rate (ticks/s) -host_mem_usage 266900 # Number of bytes of host memory used -host_seconds 6334.54 # Real time elapsed on the host +host_inst_rate 380135 # Simulator instruction rate (inst/s) +host_op_rate 409538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274873670 # Simulator tick rate (ticks/s) +host_mem_usage 314372 # Number of bytes of host memory used +host_seconds 4063.20 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory @@ -284,6 +285,7 @@ system.physmem_1.memoryStateTime::REF 37294400000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 239639355 # Number of BP lookups system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect @@ -298,6 +300,7 @@ system.cpu.branchPred.indirectHits 230 # Nu system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -327,6 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,6 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,6 +421,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 2233731337 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -461,6 +468,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 1664032481 # Class of committed instruction system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9221041 # number of replacements system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. @@ -478,6 +486,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits @@ -598,6 +607,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 29 # number of replacements system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. @@ -614,6 +624,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 753 system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits @@ -682,6 +693,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 2013919 # number of replacements system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. @@ -704,6 +716,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits @@ -856,6 +869,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution @@ -888,6 +902,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1228500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1245432 # Transaction distribution system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution system.membus.trans_dist::CleanEvict 962724 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index d2e653fdf..bd5e79823 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.767804 # Nu sim_ticks 767803843500 # Number of ticks simulated final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232866 # Simulator instruction rate (inst/s) -host_op_rate 250878 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115757951 # Simulator tick rate (ticks/s) -host_mem_usage 355612 # Number of bytes of host memory used -host_seconds 6632.84 # Real time elapsed on the host +host_inst_rate 232978 # Simulator instruction rate (inst/s) +host_op_rate 250999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 115813638 # Simulator tick rate (ticks/s) +host_mem_usage 356264 # Number of bytes of host memory used +host_seconds 6629.65 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory @@ -298,6 +299,7 @@ system.physmem_1.memoryStateTime::REF 25638600000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 286292198 # Number of BP lookups system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect @@ -312,6 +314,7 @@ system.cpu.branchPred.indirectHits 1888 # Nu system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,6 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,6 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,6 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -429,6 +435,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1535607688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -718,6 +725,7 @@ system.cpu.cc_regfile_reads 6965778765 # nu system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 17003710 # number of replacements system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits @@ -861,6 +870,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 589 # number of replacements system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. @@ -877,6 +887,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 441 system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits @@ -951,12 +962,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 4706089 # number of replacements system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. @@ -984,6 +997,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits @@ -1169,6 +1183,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution @@ -1207,6 +1222,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1613498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3696594 # Transaction distribution system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index cac059bf6..9d26db066 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490500 # Number of ticks simulated final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2181717 # Simulator instruction rate (inst/s) -host_op_rate 2350469 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175236125 # Simulator tick rate (ticks/s) -host_mem_usage 301652 # Number of bytes of host memory used -host_seconds 707.96 # Real time elapsed on the host +host_inst_rate 2178318 # Simulator instruction rate (inst/s) +host_op_rate 2346807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1173405208 # Simulator tick rate (ticks/s) +host_mem_usage 302320 # Number of bytes of host memory used +host_seconds 709.06 # Real time elapsed on the host sim_insts 1544563042 # Number of instructions simulated sim_ops 1664032434 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 750174605 # Wr system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 1664034982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution system.membus.trans_dist::ReadResp 1999474786 # Transaction distribution system.membus.trans_dist::WriteReq 172586047 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index e1d79bb9d..59601069e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1359798 # Simulator instruction rate (inst/s) -host_op_rate 1465373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2100575394 # Simulator tick rate (ticks/s) -host_mem_usage 311664 # Number of bytes of host memory used -host_seconds 1131.61 # Real time elapsed on the host +host_inst_rate 1373046 # Simulator instruction rate (inst/s) +host_op_rate 1479650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2121040557 # Simulator tick rate (ticks/s) +host_mem_usage 312336 # Number of bytes of host memory used +host_seconds 1120.69 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory @@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks 27493190 # To system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -154,6 +160,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 4754059341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9111140 # number of replacements system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. @@ -232,6 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits @@ -342,6 +351,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 7 # number of replacements system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. @@ -358,6 +368,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 606 system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits @@ -426,6 +437,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919027 # number of replacements system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks. @@ -448,6 +460,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits @@ -594,6 +607,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1151 system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution @@ -626,6 +640,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 957000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 2377029670500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169580 # Transaction distribution system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution system.membus.trans_dist::CleanEvict 897056 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 65376a235..3f6006735 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 786137 # Simulator instruction rate (inst/s) -host_op_rate 1224873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 743780816 # Simulator tick rate (ticks/s) -host_mem_usage 258352 # Number of bytes of host memory used -host_seconds 3826.41 # Real time elapsed on the host +host_inst_rate 1672243 # Simulator instruction rate (inst/s) +host_op_rate 2605507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582143797 # Simulator tick rate (ticks/s) +host_mem_usage 305608 # Number of bytes of host memory used +host_seconds 1798.83 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution system.membus.trans_dist::WriteReq 438528338 # Transaction distribution diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index e4e1963fc..5b0c36dc3 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 5.895948 # Nu sim_ticks 5895947852500 # Number of ticks simulated final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 545612 # Simulator instruction rate (inst/s) -host_op_rate 850113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1069419451 # Simulator tick rate (ticks/s) -host_mem_usage 268340 # Number of bytes of host memory used -host_seconds 5513.22 # Real time elapsed on the host +host_inst_rate 1001702 # Simulator instruction rate (inst/s) +host_op_rate 1560742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1963371956 # Simulator tick rate (ticks/s) +host_mem_usage 316648 # Number of bytes of host memory used +host_seconds 3002.97 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory @@ -36,9 +37,14 @@ system.physmem.bw_total::writebacks 11096858 # To system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 11791895705 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -99,6 +105,7 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 9108581 # number of replacements system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. @@ -117,6 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits @@ -205,6 +213,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -220,6 +229,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 632 system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 8026466439 # Number of tag accesses system.cpu.icache.tags.data_accesses 8026466439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4013232207 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232207 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232207 # number of demand (read+write) hits @@ -288,6 +298,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 1919169 # number of replacements system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. @@ -310,6 +321,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits @@ -452,6 +464,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution @@ -484,6 +497,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 5895947852500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 1169437 # Transaction distribution system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution system.membus.trans_dist::CleanEvict 896090 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 05e39f173..fcad1aab0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.051906 # Nu sim_ticks 51905634500 # Number of ticks simulated final_tick 51905634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 261291 # Simulator instruction rate (inst/s) -host_op_rate 261291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147573427 # Simulator tick rate (ticks/s) -host_mem_usage 252408 # Number of bytes of host memory used -host_seconds 351.73 # Real time elapsed on the host +host_inst_rate 509703 # Simulator instruction rate (inst/s) +host_op_rate 509703 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287873591 # Simulator tick rate (ticks/s) +host_mem_usage 300976 # Number of bytes of host memory used +host_seconds 180.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory system.physmem.bytes_read::total 340480 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 1733160000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1011440250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 11440185 # Number of BP lookups system.cpu.branchPred.condPredicted 8207191 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765027 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 51905634500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 103811269 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -343,6 +346,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 91903089 # Class of committed instruction system.cpu.tickCycles 102098443 # Number of cycles that the object actually ticked system.cpu.idleCycles 1712826 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.tagsinuse 1447.414267 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26572424 # Total number of references to valid blocks. @@ -361,6 +365,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 53153936 # Number of tag accesses system.cpu.dcache.tags.data_accesses 53153936 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20074229 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20074229 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498195 # number of WriteReq hits @@ -457,6 +462,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13853 # number of replacements system.cpu.icache.tags.tagsinuse 1642.330146 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22935687 # Total number of references to valid blocks. @@ -475,6 +481,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 946 system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 45918830 # Number of tag accesses system.cpu.icache.tags.data_accesses 45918830 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 22935687 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22935687 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22935687 # number of demand (read+write) hits @@ -543,6 +550,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269 system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2479.710860 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26619 # Total number of references to valid blocks. @@ -565,6 +573,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2507 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111908 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261876 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261876 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 13853 # number of WritebackClean hits @@ -705,6 +714,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 16303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13853 # Transaction distribution @@ -737,6 +747,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 23727000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 51905634500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3601 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 685087aff..1294dcd91 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.021909 # Nu sim_ticks 21909208500 # Number of ticks simulated final_tick 21909208500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161119 # Simulator instruction rate (inst/s) -host_op_rate 161119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41933875 # Simulator tick rate (ticks/s) -host_mem_usage 253948 # Number of bytes of host memory used -host_seconds 522.47 # Real time elapsed on the host +host_inst_rate 299674 # Simulator instruction rate (inst/s) +host_op_rate 299674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77995222 # Simulator tick rate (ticks/s) +host_mem_usage 302008 # Number of bytes of host memory used +host_seconds 280.90 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory system.physmem.bytes_read::total 334528 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 731380000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 632027000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 16102191 # Number of BP lookups system.cpu.branchPred.condPredicted 11688099 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 930994 # Number of conditional branches incorrect @@ -297,6 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 21909208500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 43818418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -589,6 +592,7 @@ system.cpu.fp_regfile_reads 6263399 # nu system.cpu.fp_regfile_writes 6178143 # number of floating regfile writes system.cpu.misc_regfile_reads 719113 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 158 # number of replacements system.cpu.dcache.tags.tagsinuse 1457.375474 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 28588753 # Total number of references to valid blocks. @@ -606,6 +610,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 57198843 # Number of tag accesses system.cpu.dcache.tags.data_accesses 57198843 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 22095651 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 22095651 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492632 # number of WriteReq hits @@ -722,6 +727,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150 system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9515 # number of replacements system.cpu.icache.tags.tagsinuse 1600.928709 # Cycle average of tags in use system.cpu.icache.tags.total_refs 15918297 # Total number of references to valid blocks. @@ -740,6 +746,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 944 system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 31876857 # Number of tag accesses system.cpu.icache.tags.data_accesses 31876857 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 15918297 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 15918297 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 15918297 # number of demand (read+write) hits @@ -814,6 +821,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858 system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2407.364249 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 18027 # Total number of references to valid blocks. @@ -836,6 +844,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109528 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 192294 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 192294 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9515 # number of WritebackClean hits @@ -976,6 +985,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 11969 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9515 # Transaction distribution @@ -1008,6 +1018,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 17179500 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 21909208500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3524 # Transaction distribution system.membus.trans_dist::ReadExReq 1703 # Transaction distribution system.membus.trans_dist::ReadExResp 1703 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 28e1374ff..31e90a11a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.130383 # Nu sim_ticks 130382890500 # Number of ticks simulated final_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181123 # Simulator instruction rate (inst/s) -host_op_rate 190933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137045131 # Simulator tick rate (ticks/s) -host_mem_usage 270196 # Number of bytes of host memory used -host_seconds 951.39 # Real time elapsed on the host +host_inst_rate 369340 # Simulator instruction rate (inst/s) +host_op_rate 389344 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279457902 # Simulator tick rate (ticks/s) +host_mem_usage 317800 # Number of bytes of host memory used +host_seconds 466.56 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247424 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 4353700000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 49622074 # Number of BP lookups system.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 207973 # Nu system.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,6 +387,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 130382890500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 260765781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -427,6 +434,7 @@ system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class_0::total 181650743 # Class of committed instruction system.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked system.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements system.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. @@ -445,6 +453,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses system.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits @@ -565,6 +574,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2881 # number of replacements system.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use system.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. @@ -583,6 +593,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses system.cpu.icache.tags.data_accesses 141572827 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits @@ -651,6 +662,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. @@ -673,6 +685,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits @@ -823,6 +836,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution @@ -855,6 +869,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7016498 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 130382890500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2775 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a41b2e194..f718004ff 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.084938 # Nu sim_ticks 84937723500 # Number of ticks simulated final_tick 84937723500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205804 # Simulator instruction rate (inst/s) -host_op_rate 216952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 101452217 # Simulator tick rate (ticks/s) -host_mem_usage 314712 # Number of bytes of host memory used -host_seconds 837.22 # Real time elapsed on the host +host_inst_rate 205612 # Simulator instruction rate (inst/s) +host_op_rate 216749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101357587 # Simulator tick rate (ticks/s) +host_mem_usage 315376 # Number of bytes of host memory used +host_seconds 838.00 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 587328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 132096 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 70976 # Number of bytes read from this memory @@ -254,6 +255,7 @@ system.physmem_1.memoryStateTime::REF 2836080000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 2138239588 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 85626366 # Number of BP lookups system.cpu.branchPred.condPredicted 68177013 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5935452 # Number of conditional branches incorrect @@ -268,6 +270,7 @@ system.cpu.branchPred.indirectHits 653746 # Nu system.cpu.branchPred.indirectMisses 27943 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 40316 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -297,6 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,6 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,6 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,6 +391,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 84937723500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 169875448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -676,6 +683,7 @@ system.cpu.cc_regfile_reads 708194084 # nu system.cpu.cc_regfile_writes 229512691 # number of cc regfile writes system.cpu.misc_regfile_reads 57440840 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 72581 # number of replacements system.cpu.dcache.tags.tagsinuse 511.413915 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 41031177 # Total number of references to valid blocks. @@ -694,6 +702,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 82360603 # Number of tag accesses system.cpu.dcache.tags.data_accesses 82360603 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 28644947 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 28644947 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12341311 # number of WriteReq hits @@ -824,6 +833,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297 system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 53623 # number of replacements system.cpu.icache.tags.tagsinuse 510.594536 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78269055 # Total number of references to valid blocks. @@ -842,6 +852,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 51 system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156707315 # Number of tag accesses system.cpu.icache.tags.data_accesses 156707315 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78269055 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78269055 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78269055 # number of demand (read+write) hits @@ -916,12 +927,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853 system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 9269 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 9269 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2141.370901 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 157591 # Total number of references to valid blocks. @@ -948,6 +961,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015503 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.179688 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3955418 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3955418 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 64698 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 64698 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 51033 # number of WritebackClean hits @@ -1112,6 +1126,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10473 system.cpu.toL2Bus.snoop_filter.tot_snoops 11905 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3377 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 118606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 64698 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 61506 # Transaction distribution @@ -1145,6 +1160,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 81207989 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 109644490 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 84937723500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 12116 # Transaction distribution system.membus.trans_dist::ReadExReq 234 # Transaction distribution system.membus.trans_dist::ReadExResp 234 # Transaction distribution diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 87cd506ee..145f8838d 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.103324 # Nu sim_ticks 103324153500 # Number of ticks simulated final_tick 103324153500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48808 # Simulator instruction rate (inst/s) -host_op_rate 81806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38183996 # Simulator tick rate (ticks/s) -host_mem_usage 302208 # Number of bytes of host memory used -host_seconds 2705.95 # Real time elapsed on the host +host_inst_rate 98344 # Simulator instruction rate (inst/s) +host_op_rate 164833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76937982 # Simulator tick rate (ticks/s) +host_mem_usage 350904 # Number of bytes of host memory used +host_seconds 1342.95 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 231488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 130496 # Number of bytes read from this memory system.physmem.bytes_read::total 361984 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 3450200000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 1069805000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 40908032 # Number of BP lookups system.cpu.branchPred.condPredicted 40908032 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6741329 # Number of conditional branches incorrect @@ -264,8 +266,12 @@ system.cpu.branchPred.indirectHits 9869044 # Nu system.cpu.branchPred.indirectMisses 25447446 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 5035252 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 103324153500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 206648308 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -560,6 +566,7 @@ system.cpu.cc_regfile_reads 107017358 # nu system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 72 # number of replacements system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks. @@ -578,6 +585,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits @@ -674,6 +682,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6515 # number of replacements system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks. @@ -692,6 +701,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 736 system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits @@ -766,6 +776,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks. @@ -788,6 +799,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits @@ -944,6 +956,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution @@ -978,6 +991,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 13500000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3422499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 103324153500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4149 # Transaction distribution system.membus.trans_dist::UpgradeReq 500 # Transaction distribution system.membus.trans_dist::ReadExReq 1507 # Transaction distribution |